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phy/trionrgmii,titaniumrgmii: replaces str by ClockSignal for ClkInput and PLL

This commit is contained in:
Gwenhael Goavec-Merou 2024-09-26 11:03:12 +02:00
parent 2b0156e9b3
commit 3696ef82bb
2 changed files with 4 additions and 4 deletions
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4
liteeth/phy/titaniumrgmii.py
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@ -131,7 +131,7 @@ class LiteEthPHYRGMIICRG(LiteXModule):
# -------
self.specials += ClkInput(
i = clock_pads.rx,
o = f"auto_eth{n}_rx_clk_in", # FIXME: Use Clk Signal.
o = self.cd_eth_rx.clk,
)
# TX Clk.
@ -144,7 +144,7 @@ class LiteEthPHYRGMIICRG(LiteXModule):
# TX PLL.
# -------
self.pll = pll = TITANIUMPLL(platform)
pll.register_clkin(None, freq=125e6, name=f"auto_eth{n}_rx_clk_in0") # FIXME: 0 is to match ClkInput
pll.register_clkin(self.cd_eth_rx.clk, freq=125e6)
pll.create_clkout(self.cd_eth_rx, freq=125e6, phase=0, with_reset=False)
pll.create_clkout(self.cd_eth_tx, freq=125e6, phase=0, with_reset=False)
pll.create_clkout(self.cd_eth_tx_delayed, freq=125e6, phase=90)

4
liteeth/phy/trionrgmii.py
View File

@ -131,7 +131,7 @@ class LiteEthPHYRGMIICRG(LiteXModule):
# -------
self.specials += ClkInput(
i = clock_pads.rx,
o = f"auto_eth{n}_rx_clk_in", # FIXME: Use Clk Signal.
o = self.cd_eth_rx.clk,
)
# TX Clk.
@ -144,7 +144,7 @@ class LiteEthPHYRGMIICRG(LiteXModule):
# TX PLL.
# -------
self.pll = pll = TRIONPLL(platform)
pll.register_clkin(None, freq=125e6, name=f"auto_eth{n}_rx_clk_in0") # FIXME: 0 is to match ClkInput
pll.register_clkin(self.cd_eth_rx.clk, freq=125e6)
pll.create_clkout(self.cd_eth_rx, freq=125e6, phase=0, with_reset=False, is_feedback=True)
pll.create_clkout(self.cd_eth_tx, freq=125e6, phase=0, with_reset=False)
pll.create_clkout(self.cd_eth_tx_delayed, freq=125e6, phase=45)