From 3a54bf2b8b861f21c84d62ae6352da293ef380de Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Sat, 18 Jan 2020 00:24:22 +0100 Subject: [PATCH] phy/rgmiis: uniformize a bit more --- liteeth/phy/ecp5rgmii.py | 4 ++-- liteeth/phy/s6rgmii.py | 2 +- liteeth/phy/s7rgmii.py | 5 ++--- liteeth/phy/usrgmii.py | 25 +++++++++++-------------- 4 files changed, 16 insertions(+), 20 deletions(-) diff --git a/liteeth/phy/ecp5rgmii.py b/liteeth/phy/ecp5rgmii.py index d0c2d2e..cac770c 100644 --- a/liteeth/phy/ecp5rgmii.py +++ b/liteeth/phy/ecp5rgmii.py @@ -160,7 +160,7 @@ class LiteEthPHYRGMIICRG(Module, AutoCSR): ] # Reset - reset = Signal() + self.reset = reset = Signal() if with_hw_init_reset: self.submodules.hw_reset = LiteEthPHYHWReset() self.comb += reset.eq(self._reset.storage | self.hw_reset.reset) @@ -179,7 +179,7 @@ class LiteEthPHYRGMII(Module, AutoCSR): def __init__(self, clock_pads, pads, with_hw_init_reset=True, tx_delay=2e-9, rx_delay=2e-9): self.submodules.crg = LiteEthPHYRGMIICRG(clock_pads, pads, with_hw_init_reset, tx_delay) self.submodules.tx = ClockDomainsRenamer("eth_tx")(LiteEthPHYRGMIITX(pads)) - self.submodules.rx = ClockDomainsRenamer("eth_rx")(LiteEthPHYRGMIIRX(pads, tx_delay)) + self.submodules.rx = ClockDomainsRenamer("eth_rx")(LiteEthPHYRGMIIRX(pads, rx_delay)) self.sink, self.source = self.tx.sink, self.rx.source if hasattr(pads, "mdc"): diff --git a/liteeth/phy/s6rgmii.py b/liteeth/phy/s6rgmii.py index d07112a..6f97765 100644 --- a/liteeth/phy/s6rgmii.py +++ b/liteeth/phy/s6rgmii.py @@ -231,7 +231,7 @@ class LiteEthPHYRGMIICRG(Module, AutoCSR): ] # Reset - reset = Signal() + self.reset = reset = Signal() if with_hw_init_reset: self.submodules.hw_reset = LiteEthPHYHWReset() self.comb += reset.eq(self._reset.storage | self.hw_reset.reset) diff --git a/liteeth/phy/s7rgmii.py b/liteeth/phy/s7rgmii.py index f213beb..25cf00b 100644 --- a/liteeth/phy/s7rgmii.py +++ b/liteeth/phy/s7rgmii.py @@ -105,7 +105,6 @@ class LiteEthPHYRGMIICRG(Module, AutoCSR): self.clock_domains.cd_eth_tx = ClockDomain() self.clock_domains.cd_eth_tx_delayed = ClockDomain(reset_less=True) - # RX eth_rx_clk_ibuf = Signal() self.specials += [ @@ -139,8 +138,8 @@ class LiteEthPHYRGMIICRG(Module, AutoCSR): self.comb += reset.eq(self._reset.storage | self.hw_reset.reset) else: self.comb += reset.eq(self._reset.storage) - - self.comb += pads.rst_n.eq(~reset) + if hasattr(pads, "rst_n"): + self.comb += pads.rst_n.eq(~reset) self.specials += [ AsyncResetSynchronizer(self.cd_eth_tx, reset), AsyncResetSynchronizer(self.cd_eth_rx, reset), diff --git a/liteeth/phy/usrgmii.py b/liteeth/phy/usrgmii.py index 80648fb..c7e8d01 100644 --- a/liteeth/phy/usrgmii.py +++ b/liteeth/phy/usrgmii.py @@ -129,7 +129,10 @@ class LiteEthPHYRGMIIRX(Module): last = Signal() self.comb += last.eq(~rx_ctl & rx_ctl_d) - self.sync += [source.valid.eq(rx_ctl), source.data.eq(rx_data)] + self.sync += [ + source.valid.eq(rx_ctl), + source.data.eq(rx_data) + ] self.comb += source.last.eq(last) @@ -146,12 +149,8 @@ class LiteEthPHYRGMIICRG(Module, AutoCSR): # RX eth_rx_clk_ibuf = Signal() self.specials += [ - Instance("IBUF", - i_I=clock_pads.rx, - o_O=eth_rx_clk_ibuf), - Instance("BUFG", - i_I=eth_rx_clk_ibuf, - o_O=self.cd_eth_rx.clk) + Instance("IBUF", i_I=clock_pads.rx, o_O=eth_rx_clk_ibuf), + Instance("BUFG", i_I=eth_rx_clk_ibuf, o_O=self.cd_eth_rx.clk) ] # TX @@ -175,16 +174,14 @@ class LiteEthPHYRGMIICRG(Module, AutoCSR): ] # Reset - reset = Signal() + self.reset = reset = Signal() if with_hw_init_reset: self.submodules.hw_reset = LiteEthPHYHWReset() self.comb += reset.eq(self._reset.storage | self.hw_reset.reset) else: self.comb += reset.eq(self._reset.storage) - - if hasattr(pads, 'rst_n'): - self.comb += pads.rst_n.eq(1) - + if hasattr(pads, "rst_n"): + self.comb += pads.rst_n.eq(~reset) self.specials += [ AsyncResetSynchronizer(self.cd_eth_tx, reset), AsyncResetSynchronizer(self.cd_eth_rx, reset), @@ -195,8 +192,8 @@ class LiteEthPHYRGMII(Module, AutoCSR): dw = 8 def __init__(self, clock_pads, pads, with_hw_init_reset=True, tx_delay=2e-9, rx_delay=2e-9): self.submodules.crg = LiteEthPHYRGMIICRG(clock_pads, pads, with_hw_init_reset, tx_delay) - self.submodules.tx = ClockDomainsRenamer("eth_tx")(LiteEthPHYRGMIITX(pads)) - self.submodules.rx = ClockDomainsRenamer("eth_rx")(LiteEthPHYRGMIIRX(pads, rx_delay)) + self.submodules.tx = ClockDomainsRenamer("eth_tx")(LiteEthPHYRGMIITX(pads)) + self.submodules.rx = ClockDomainsRenamer("eth_rx")(LiteEthPHYRGMIIRX(pads, rx_delay)) self.sink, self.source = self.tx.sink, self.rx.source if hasattr(pads, "mdc"):