diff --git a/liteeth/phy/titaniumrgmii.py b/liteeth/phy/titaniumrgmii.py
index 987f5b9..739e1e3 100644
--- a/liteeth/phy/titaniumrgmii.py
+++ b/liteeth/phy/titaniumrgmii.py
@@ -22,7 +22,7 @@ from liteeth.phy.common import *
 # LiteEth PHY RGMII TX -----------------------------------------------------------------------------
 
 class LiteEthPHYRGMIITX(LiteXModule):
-    def __init__(self, platform, pads, ddr_tx_ctl=True):
+    def __init__(self, platform, pads):
         self.sink = sink = stream.Endpoint(eth_phy_description(8))
 
         # # #
@@ -36,31 +36,27 @@ class LiteEthPHYRGMIITX(LiteXModule):
                 i1  = tx_data_h[n],
                 i2  = tx_data_l[n],
                 o   = pads.tx_data[n],
-                clk = "auto_eth_tx_clk", # FIXME.
+                clk = "auto_eth_tx_clk", # FIXME: Use Clk Signal.
             )
 
         # TX Ctl IOs.
         # -----------
-        if ddr_tx_ctl:
-            tx_ctl_h = Signal()
-            tx_ctl_l = Signal()
-            self.specials += DDROutput(
-                i1  = tx_ctl_h,
-                i2  = tx_ctl_l,
-                o   = pads.tx_ctl,
-                clk = "auto_eth_tx_clk", # FIXME.
-            )
-        else:
-            self.sync.eth_tx += pads.tx_ctl.eq(sink.valid)
+        tx_ctl_h = Signal()
+        tx_ctl_l = Signal()
+        self.specials += DDROutput(
+            i1  = tx_ctl_h,
+            i2  = tx_ctl_l,
+            o   = pads.tx_ctl,
+            clk = "auto_eth_tx_clk", # FIXME: Use Clk Signal.
+        )
 
         # Logic.
         # ------
         self.comb += sink.ready.eq(1)
-        if ddr_tx_ctl:
-            self.sync += [
-                tx_ctl_h.eq(sink.valid),
-                tx_ctl_l.eq(sink.valid),
-            ]
+        self.sync += [
+            tx_ctl_h.eq(sink.valid),
+            tx_ctl_l.eq(sink.valid),
+        ]
         for n in range(4):
             self.sync += [
                 tx_data_h[n].eq(sink.data[n + 0]),
@@ -84,25 +80,36 @@ class LiteEthPHYRGMIIRX(LiteXModule):
                 i   = pads.rx_data[n],
                 o1  = rx_data_h[n],
                 o2  = rx_data_l[n],
-                clk = "auto_eth_rx_clk", # FIXME.
+                clk = "auto_eth_rx_clk", # FIXME: Use Clk Signal.
             )
 
         # RX Ctl IOs.
         # -----------
+        rx_ctl_h = Signal()
+        rx_ctl_l = Signal()
+        self.specials += DDRInput(
+            i   = pads.rx_ctl,
+            o1  = rx_ctl_h,
+            o2  = rx_ctl_l,
+            clk = "auto_eth_rx_clk", # FIXME: Use Clk Signal.
+        )
+
+        rx_ctl   = rx_ctl_h
         rx_ctl_d = Signal()
-        self.sync += rx_ctl_d.eq(pads.rx_ctl)
+        self.sync += rx_ctl_d.eq(rx_ctl)
 
         # Logic.
         # ------
         last    = Signal()
-        rx_data = Signal(8)
+        rx_data_lsb = Signal(4)
+        rx_data_msb = Signal(4)
         for n in range(4):
-            self.comb += rx_data[n + 0].eq(rx_data_l[n])
-            self.comb += rx_data[n + 4].eq(rx_data_h[n])
-        self.comb += last.eq(~pads.rx_ctl & rx_ctl_d)
+            self.comb += rx_data_msb[n + 0].eq(rx_data_l[n])
+            self.sync += rx_data_lsb[n + 0].eq(rx_data_h[n])
         self.sync += [
+            last.eq(~rx_ctl & rx_ctl_d),
             source.valid.eq(rx_ctl_d),
-            source.data.eq(rx_data),
+            source.data.eq(Cat(rx_data_lsb, rx_data_msb)),
         ]
         self.comb += source.last.eq(last)
 
@@ -121,7 +128,7 @@ class LiteEthPHYRGMIICRG(LiteXModule):
 
         # RX Clk.
         # -------
-        eth_rx_clk = platform.add_iface_io("auto_eth_rx_clk")
+        eth_rx_clk = platform.add_iface_io("auto_eth_rx_clk_in")
         block = {
             "type"       : "GPIO",
             "size"       : 1,
@@ -132,10 +139,6 @@ class LiteEthPHYRGMIICRG(LiteXModule):
         }
         platform.toolchain.ifacewriter.blocks.append(block)
         platform.toolchain.excluded_ios.append(clock_pads.rx)
-        self.comb += self.cd_eth_rx.clk.eq(eth_rx_clk)
-
-        cmd = "create_clock -period {} auto_eth_rx_clk".format(1e9/125e6)
-        platform.toolchain.additional_sdc_commands.append(cmd)
 
         # TX Clk.
         # -------
@@ -153,12 +156,10 @@ class LiteEthPHYRGMIICRG(LiteXModule):
         # TX PLL.
         # -------
         self.pll = pll = TITANIUMPLL(platform, n=1) # FIXME: Add Auto-Numbering.
-        pll.register_clkin(None,          freq=125e6,           name="auto_eth_rx_clk")
-        pll.create_clkout(None,           freq=125e6,           name="auto_eth_tx_clk")
-        pll.create_clkout(self.cd_eth_tx, freq=125e6,  phase=0, name="auto_eth_tx_clk_delayed", with_reset=False)
-
-        cmd = "create_clock -period {} eth_tx_clk".format(1e9/125e6)
-        platform.toolchain.additional_sdc_commands.append(cmd)
+        pll.register_clkin(None,          freq=125e6,           name="auto_eth_rx_clk_in")
+        pll.create_clkout(self.cd_eth_rx, freq=125e6, phase=0,  name="auto_eth_rx_clk", with_reset=False)
+        pll.create_clkout(self.cd_eth_tx, freq=125e6, phase=0,  name="auto_eth_tx_clk", with_reset=False)
+        pll.create_clkout(None,           freq=125e6, phase=90, name="auto_eth_tx_clk_delayed")
 
         # Reset.
         # ------
@@ -181,8 +182,7 @@ class LiteEthPHYRGMII(LiteXModule):
     dw          = 8
     tx_clk_freq = 125e6
     rx_clk_freq = 125e6
-    def __init__(self, platform, clock_pads, pads, with_hw_init_reset=True,
-            iodelay_clk_freq=200e6, hw_reset_cycles=256):
+    def __init__(self, platform, clock_pads, pads, with_hw_init_reset=True, hw_reset_cycles=256):
         self.crg = LiteEthPHYRGMIICRG(platform, clock_pads, with_hw_init_reset, hw_reset_cycles)
         self.tx  = ClockDomainsRenamer("eth_tx")(LiteEthPHYRGMIITX(platform, pads))
         self.rx  = ClockDomainsRenamer("eth_rx")(LiteEthPHYRGMIIRX(platform, pads))