diff --git a/bench/sim.py b/bench/sim.py
new file mode 100755
index 0000000..7128733
--- /dev/null
+++ b/bench/sim.py
@@ -0,0 +1,87 @@
+#!/usr/bin/env python3
+
+#
+# This file is part of LiteEth.
+#
+# Copyright (c) 2020 Florent Kermarrec <florent@enjoy-digital.fr>
+# SPDX-License-Identifier: BSD-2-Clause
+
+import argparse
+
+from migen import *
+
+from litex.build.generic_platform import *
+from litex.build.sim import SimPlatform
+from litex.build.sim.config import SimConfig
+
+from litex.soc.integration.soc_core import *
+from litex.soc.integration.builder import *
+
+from liteeth.phy.model import LiteEthPHYModel
+
+# IOs ----------------------------------------------------------------------------------------------
+
+_io = [
+    ("sys_clk", 0, Pins(1)),
+    ("sys_rst", 0, Pins(1)),
+    ("eth_clocks", 0,
+        Subsignal("tx", Pins(1)),
+        Subsignal("rx", Pins(1)),
+    ),
+    ("eth", 0,
+        Subsignal("source_valid", Pins(1)),
+        Subsignal("source_ready", Pins(1)),
+        Subsignal("source_data",  Pins(8)),
+
+        Subsignal("sink_valid",   Pins(1)),
+        Subsignal("sink_ready",   Pins(1)),
+        Subsignal("sink_data",    Pins(8)),
+    ),
+]
+
+# Platform -----------------------------------------------------------------------------------------
+
+class Platform(SimPlatform):
+    def __init__(self):
+        SimPlatform.__init__(self, "SIM", _io)
+
+# Bench SoC ----------------------------------------------------------------------------------------
+
+class BenchSoC(SoCCore):
+    def __init__(self, **kwargs):
+        platform     = Platform()
+        sys_clk_freq = int(1e6)
+
+        # SoCMini ----------------------------------------------------------------------------------
+        SoCMini.__init__(self, platform, clk_freq=sys_clk_freq,
+            ident          = "LiteEth bench Simulation",
+            ident_version  = True
+        )
+
+        # CRG --------------------------------------------------------------------------------------
+        self.submodules.crg = CRG(platform.request("sys_clk"))
+
+        # Etherbone --------------------------------------------------------------------------------
+        self.submodules.ethphy = LiteEthPHYModel(self.platform.request("eth"))
+        self.add_csr("ethphy")
+        self.add_etherbone(phy=self.ethphy, buffer_depth=255)
+
+        # SRAM -------------------------------------------------------------------------------------
+        self.add_ram("sram", 0x20000000, 0x1000)
+
+# Main ---------------------------------------------------------------------------------------------
+
+def main():
+    parser = argparse.ArgumentParser(description="LiteEth Bench Simulation")
+    args = parser.parse_args()
+
+    sim_config = SimConfig()
+    sim_config.add_clocker("sys_clk", freq_hz=1e6)
+    sim_config.add_module("ethernet", "eth", args={"interface": "tap0", "ip": "192.168.1.50"})
+
+    soc     = BenchSoC()
+    builder = Builder(soc, csr_csv="csr.csv")
+    builder.build(sim_config=sim_config)
+
+if __name__ == "__main__":
+    main()