From 3e026795d8188b96ec9e25496ece5026bef801cd Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Tue, 13 Jun 2023 18:22:47 +0200
Subject: [PATCH] bench/xcu1525/xu8_st1: Directly add IOs in Etherbone section.

---
 bench/xcu1525.py | 24 +++++++++++-------------
 bench/xu8_st1.py | 24 +++++++++++-------------
 2 files changed, 22 insertions(+), 26 deletions(-)

diff --git a/bench/xcu1525.py b/bench/xcu1525.py
index 50ac367..5cf08d7 100755
--- a/bench/xcu1525.py
+++ b/bench/xcu1525.py
@@ -24,18 +24,6 @@ from litex.soc.integration.builder import *
 
 from liteeth.phy.usp_gty_1000basex import USP_GTY_1000BASEX
 
-# IOs ----------------------------------------------------------------------------------------------
-
-_qsfp_io = [
-    # QSFP0
-    ("qsfp", 0,
-        Subsignal("txp", Pins("N9")),
-        Subsignal("txn", Pins("N8")),
-        Subsignal("rxp", Pins("N4")),
-        Subsignal("rxn", Pins("N3"))
-    ),
-]
-
 # CRG ----------------------------------------------------------------------------------------------
 
 class _CRG(LiteXModule):
@@ -56,7 +44,6 @@ class _CRG(LiteXModule):
 class BenchSoC(SoCCore):
     def __init__(self, sys_clk_freq=int(125e6)):
         platform = sqrl_xcu1525.Platform()
-        platform.add_extension(_qsfp_io)
 
         # SoCMini ----------------------------------------------------------------------------------
         SoCMini.__init__(self, platform, clk_freq=sys_clk_freq,
@@ -68,6 +55,17 @@ class BenchSoC(SoCCore):
         self.crg = _CRG(platform, sys_clk_freq)
 
         # Etherbone --------------------------------------------------------------------------------
+
+        platform.add_extension([
+            # SFP.
+            ("qsfp", 0,
+                Subsignal("txp", Pins("N9")),
+                Subsignal("txn", Pins("N8")),
+                Subsignal("rxp", Pins("N4")),
+                Subsignal("rxn", Pins("N3"))
+            )
+        ])
+
         self.ethphy = USP_GTY_1000BASEX(self.crg.cd_eth.clk,
             data_pads    = self.platform.request("qsfp", 0),
             sys_clk_freq = self.clk_freq)
diff --git a/bench/xu8_st1.py b/bench/xu8_st1.py
index 8484e21..5f4ec93 100755
--- a/bench/xu8_st1.py
+++ b/bench/xu8_st1.py
@@ -24,18 +24,6 @@ from litex.soc.integration.builder import *
 
 from liteeth.phy.usp_gth_1000basex import USP_GTH_1000BASEX
 
-# IOs ----------------------------------------------------------------------------------------------
-
-_sfp_io = [
-    # SFP.
-    ("sfp", 0,
-        Subsignal("txp", Pins("K6")),
-        Subsignal("txn", Pins("K5")),
-        Subsignal("rxp", Pins("J4")),
-        Subsignal("rxn", Pins("J3"))
-    ),
-]
-
 # CRG ----------------------------------------------------------------------------------------------
 
 class _CRG(LiteXModule):
@@ -55,7 +43,6 @@ class _CRG(LiteXModule):
 class BenchSoC(SoCCore):
     def __init__(self, sys_clk_freq=int(125e6)):
         platform = enclustra_mercury_xu8_pe3.Platform()
-        platform.add_extension(_sfp_io)
 
         # SoCMini ----------------------------------------------------------------------------------
         SoCMini.__init__(self, platform, clk_freq=sys_clk_freq,
@@ -67,6 +54,17 @@ class BenchSoC(SoCCore):
         self.crg = _CRG(platform, sys_clk_freq)
 
         # Etherbone --------------------------------------------------------------------------------
+
+        platform.add_extension([
+            # SFP.
+            ("sfp", 0,
+                Subsignal("txp", Pins("K6")),
+                Subsignal("txn", Pins("K5")),
+                Subsignal("rxp", Pins("J4")),
+                Subsignal("rxn", Pins("J3"))
+            )
+        ])
+
         self.ethphy = USP_GTH_1000BASEX(self.crg.cd_eth.clk,
             data_pads    = self.platform.request("sfp", 0),
             sys_clk_freq = self.clk_freq)