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bench/xcu1525/xu8_st1: Directly add IOs in Etherbone section.

This commit is contained in:
Florent Kermarrec 2023-06-13 18:22:47 +02:00
parent af5b9f433f
commit 3e026795d8
2 changed files with 22 additions and 26 deletions
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24
bench/xcu1525.py
View File

@ -24,18 +24,6 @@ from litex.soc.integration.builder import *
from liteeth.phy.usp_gty_1000basex import USP_GTY_1000BASEX
# IOs ----------------------------------------------------------------------------------------------
_qsfp_io = [
# QSFP0
("qsfp", 0,
Subsignal("txp", Pins("N9")),
Subsignal("txn", Pins("N8")),
Subsignal("rxp", Pins("N4")),
Subsignal("rxn", Pins("N3"))
),
]
# CRG ----------------------------------------------------------------------------------------------
class _CRG(LiteXModule):
@ -56,7 +44,6 @@ class _CRG(LiteXModule):
class BenchSoC(SoCCore):
def __init__(self, sys_clk_freq=int(125e6)):
platform = sqrl_xcu1525.Platform()
platform.add_extension(_qsfp_io)
# SoCMini ----------------------------------------------------------------------------------
SoCMini.__init__(self, platform, clk_freq=sys_clk_freq,
@ -68,6 +55,17 @@ class BenchSoC(SoCCore):
self.crg = _CRG(platform, sys_clk_freq)
# Etherbone --------------------------------------------------------------------------------
platform.add_extension([
# SFP.
("qsfp", 0,
Subsignal("txp", Pins("N9")),
Subsignal("txn", Pins("N8")),
Subsignal("rxp", Pins("N4")),
Subsignal("rxn", Pins("N3"))
)
])
self.ethphy = USP_GTY_1000BASEX(self.crg.cd_eth.clk,
data_pads = self.platform.request("qsfp", 0),
sys_clk_freq = self.clk_freq)

24
bench/xu8_st1.py
View File

@ -24,18 +24,6 @@ from litex.soc.integration.builder import *
from liteeth.phy.usp_gth_1000basex import USP_GTH_1000BASEX
# IOs ----------------------------------------------------------------------------------------------
_sfp_io = [
# SFP.
("sfp", 0,
Subsignal("txp", Pins("K6")),
Subsignal("txn", Pins("K5")),
Subsignal("rxp", Pins("J4")),
Subsignal("rxn", Pins("J3"))
),
]
# CRG ----------------------------------------------------------------------------------------------
class _CRG(LiteXModule):
@ -55,7 +43,6 @@ class _CRG(LiteXModule):
class BenchSoC(SoCCore):
def __init__(self, sys_clk_freq=int(125e6)):
platform = enclustra_mercury_xu8_pe3.Platform()
platform.add_extension(_sfp_io)
# SoCMini ----------------------------------------------------------------------------------
SoCMini.__init__(self, platform, clk_freq=sys_clk_freq,
@ -67,6 +54,17 @@ class BenchSoC(SoCCore):
self.crg = _CRG(platform, sys_clk_freq)
# Etherbone --------------------------------------------------------------------------------
platform.add_extension([
# SFP.
("sfp", 0,
Subsignal("txp", Pins("K6")),
Subsignal("txn", Pins("K5")),
Subsignal("rxp", Pins("J4")),
Subsignal("rxn", Pins("J3"))
)
])
self.ethphy = USP_GTH_1000BASEX(self.crg.cd_eth.clk,
data_pads = self.platform.request("sfp", 0),
sys_clk_freq = self.clk_freq)