From 3e8dbe23ef1a1d184a1bf0a5391de45ecda78510 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 23 Jan 2024 15:34:10 +0100 Subject: [PATCH] liteeth/phy: Add K7_2500BASEX support. --- liteeth/gen.py | 1 + liteeth/phy/__init__.py | 1 + liteeth/phy/k7_1000basex.py | 31 ++++++++++++++++++++----------- 3 files changed, 22 insertions(+), 11 deletions(-) diff --git a/liteeth/gen.py b/liteeth/gen.py index 340a85c..2bb3748 100755 --- a/liteeth/gen.py +++ b/liteeth/gen.py @@ -280,6 +280,7 @@ class PHYCore(SoCMini): liteeth_phys.A7_1000BASEX, liteeth_phys.A7_2500BASEX, liteeth_phys.K7_1000BASEX, + liteeth_phys.K7_2500BASEX, liteeth_phys.KU_1000BASEX, liteeth_phys.USP_GTH_1000BASEX, liteeth_phys.USP_GTY_1000BASEX, diff --git a/liteeth/phy/__init__.py b/liteeth/phy/__init__.py index 1b5381a..c104c4f 100644 --- a/liteeth/phy/__init__.py +++ b/liteeth/phy/__init__.py @@ -36,6 +36,7 @@ from liteeth.phy.ecp5rgmii import LiteEthPHYRGMII as LiteEthECP5PHYRGMII from liteeth.phy.a7_1000basex import A7_1000BASEX from liteeth.phy.a7_1000basex import A7_2500BASEX from liteeth.phy.k7_1000basex import K7_1000BASEX +from liteeth.phy.k7_1000basex import K7_2500BASEX from liteeth.phy.ku_1000basex import KU_1000BASEX from liteeth.phy.usp_gth_1000basex import USP_GTH_1000BASEX from liteeth.phy.usp_gty_1000basex import USP_GTY_1000BASEX diff --git a/liteeth/phy/k7_1000basex.py b/liteeth/phy/k7_1000basex.py index 1f48a62..96bb401 100644 --- a/liteeth/phy/k7_1000basex.py +++ b/liteeth/phy/k7_1000basex.py @@ -1,7 +1,7 @@ # # This file is part of MiSoC and has been adapted/modified for LiteEth. # -# Copyright (c) 2018-2020 Florent Kermarrec +# Copyright (c) 2018-2024 Florent Kermarrec # SPDX-License-Identifier: BSD-2-Clause from migen import * @@ -22,9 +22,11 @@ from liteeth.phy.pcs_1000basex import * class K7_1000BASEX(LiteXModule): # Configured for 200MHz transceiver reference clock. dw = 8 - tx_clk_freq = 125e6 + linerate = 1.25e9 rx_clk_freq = 125e6 - def __init__(self, refclk_or_clk_pads, data_pads, sys_clk_freq, with_csr=True, rx_polarity=0, tx_polarity=0): + tx_clk_freq = 125e6 + def __init__(self, refclk_or_clk_pads, data_pads, sys_clk_freq, refclk_freq=200e6, with_csr=True, rx_polarity=0, tx_polarity=0): + assert refclk_freq in [200e6] pcs = PCS(lsb_first=True) self.submodules += pcs @@ -71,7 +73,7 @@ class K7_1000BASEX(LiteXModule): rx_data = Signal(20) rx_reset_done = Signal() - pll = GTXChannelPLL(refclk, 200e6, 1.25e9) + pll = GTXChannelPLL(refclk, 200e6, self.linerate) self.submodules.pll = pll # Work around Python's 255 argument limitation. @@ -207,7 +209,7 @@ class K7_1000BASEX(LiteXModule): p_RX_DEFER_RESET_BUF_EN = "TRUE", # CDR Attributes - p_RXCDR_CFG = 0x03000023ff10100020, + p_RXCDR_CFG = 0x03000023ff10100020, # FIXME: Add 2.5Gbps config. p_RXCDR_FR_RESET_ON_EIDLE = 0b0, p_RXCDR_HOLD_DURING_EIDLE = 0b0, p_RXCDR_PH_RESET_ON_EIDLE = 0b0, @@ -723,17 +725,17 @@ class K7_1000BASEX(LiteXModule): # TX MMCM. self.tx_mmcm = tx_mmcm = S7MMCM() - tx_mmcm.register_clkin(txoutclk_rebuffer, 62.5e6) - tx_mmcm.create_clkout(self.cd_eth_tx_half, 62.5e6, buf="bufh", with_reset=False) - tx_mmcm.create_clkout(self.cd_eth_tx, 125.0e6, buf="bufh", with_reset=True) + tx_mmcm.register_clkin(txoutclk_rebuffer, self.tx_clk_freq/2) + tx_mmcm.create_clkout(self.cd_eth_tx_half, self.tx_clk_freq/2, buf="bufh", with_reset=False) + tx_mmcm.create_clkout(self.cd_eth_tx, self.tx_clk_freq, buf="bufh", with_reset=True) self.comb += tx_mmcm.reset.eq(tx_mmcm_reset) self.comb += tx_mmcm_locked.eq(tx_mmcm.locked) # RX MMCM. self.rx_mmcm = rx_mmcm = S7MMCM() - rx_mmcm.register_clkin(rxoutclk_rebuffer, 62.5e6) - rx_mmcm.create_clkout(self.cd_eth_rx_half, 62.5e6, buf="bufg", with_reset=False) - rx_mmcm.create_clkout(self.cd_eth_rx, 125.0e6, buf="bufg", with_reset=True) + rx_mmcm.register_clkin(rxoutclk_rebuffer, self.rx_clk_freq/2) + rx_mmcm.create_clkout(self.cd_eth_rx_half, self.rx_clk_freq/2, buf="bufg", with_reset=False) + rx_mmcm.create_clkout(self.cd_eth_rx, self.rx_clk_freq, buf="bufg", with_reset=True) self.comb += rx_mmcm.reset.eq(rx_mmcm_reset) self.comb += rx_mmcm_locked.eq(rx_mmcm.locked) @@ -796,3 +798,10 @@ class K7_1000BASEX(LiteXModule): def add_csr(self): self._reset = CSRStorage() self.comb += self.reset.eq(self._reset.storage) + +# K7_2500BASEX PHY --------------------------------------------------------------------------------- + +class K7_2500BASEX(K7_1000BASEX): + linerate = 2.5e9 + rx_clk_freq = 312.5e6 + tx_clk_freq = 312.5e6