From 43a2ea811819c4fa07e9b5db996a58ae8bc5db5d Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Thu, 15 Jul 2021 18:07:15 +0200 Subject: [PATCH] frontend/Etherbone: Use new LiteX's PacketFIFO. --- liteeth/frontend/etherbone.py | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/liteeth/frontend/etherbone.py b/liteeth/frontend/etherbone.py index 5c3b548..1d09de7 100644 --- a/liteeth/frontend/etherbone.py +++ b/liteeth/frontend/etherbone.py @@ -205,9 +205,11 @@ class LiteEthEtherboneRecordReceiver(Module): # # # - # TODO: optimize ressources (no need to store parameters as datas) - fifo = stream.SyncFIFO(eth_etherbone_record_description(32), buffer_depth, buffered=True) - self.submodules += fifo + self.submodules.fifo = fifo = PacketFIFO(eth_etherbone_record_description(32), + payload_depth = buffer_depth, + param_depth = 1, + buffered = True + ) self.comb += sink.connect(fifo.sink) base_addr = Signal(32, reset_less=True) @@ -279,9 +281,11 @@ class LiteEthEtherboneRecordSender(Module): # # # - # TODO: optimize ressources (no need to store parameters as datas) - fifo = PacketFIFO(eth_etherbone_mmap_description(32), buffer_depth, buffered=True) - self.submodules += fifo + self.submodules.fifo = fifo = PacketFIFO(eth_etherbone_mmap_description(32), + payload_depth = buffer_depth, + param_depth = 1, + buffered = True + ) self.comb += sink.connect(fifo.sink) self.submodules.fsm = fsm = FSM(reset_state="IDLE")