diff --git a/liteeth/common.py b/liteeth/common.py index e911e1b..e23dcdc 100644 --- a/liteeth/common.py +++ b/liteeth/common.py @@ -16,15 +16,6 @@ def reverse_bytes(signal): return Cat(*r) -@ResetInserter() -@CEInserter() -class Counter(Module): - def __init__(self, *args, increment=1, **kwargs): - self.value = Signal(*args, **kwargs) - self.width = len(self.value) - self.sync += self.value.eq(self.value+increment) - - class Port: def connect(self, port): r = [ diff --git a/liteeth/core/arp.py b/liteeth/core/arp.py index b2644ad..708a0fe 100644 --- a/liteeth/core/arp.py +++ b/liteeth/core/arp.py @@ -30,21 +30,28 @@ class LiteEthARPTX(Module): self.submodules.packetizer = packetizer = LiteEthARPPacketizer() - counter = Counter(max=max(arp_header.length, eth_min_len)) - self.submodules += counter + counter = Signal(max=max(arp_header.length, eth_min_len)) + counter_reset = Signal() + counter_ce = Signal() + self.sync += \ + If(counter_reset, + counter.eq(0) + ).Elif(counter_ce, + counter.eq(counter + 1) + ) self.submodules.fsm = fsm = FSM(reset_state="IDLE") fsm.act("IDLE", sink.ack.eq(1), - counter.reset.eq(1), + counter_reset.eq(1), If(sink.stb, sink.ack.eq(0), NextState("SEND") ) ) self.comb += [ - packetizer.sink.sop.eq(counter.value == 0), - packetizer.sink.eop.eq(counter.value == max(arp_header.length, eth_min_len)-1), + packetizer.sink.sop.eq(counter == 0), + packetizer.sink.eop.eq(counter == max(arp_header.length, eth_min_len)-1), packetizer.sink.hwtype.eq(arp_hwtype_ethernet), packetizer.sink.proto.eq(arp_proto_ip), packetizer.sink.hwsize.eq(6), @@ -69,7 +76,7 @@ class LiteEthARPTX(Module): source.sender_mac.eq(mac_address), source.ethernet_type.eq(ethernet_type_arp), If(source.stb & source.ack, - counter.ce.eq(1), + counter_ce.eq(1), If(source.eop, sink.ack.eq(1), NextState("IDLE") @@ -174,9 +181,17 @@ class LiteEthARPTable(Module): ) request_timer = WaitTimer(clk_freq//10) - request_counter = Counter(max=max_requests) - self.submodules += request_timer, request_counter - self.comb += request_timer.wait.eq(request_pending & ~request_counter.ce) + self.submodules += request_timer + request_counter = Signal(max=max_requests) + request_counter_reset = Signal() + request_counter_ce = Signal() + self.sync += \ + If(request_counter_reset, + request_counter.eq(0) + ).Elif(request_counter_ce, + request_counter.eq(request_counter + 1) + ) + self.comb += request_timer.wait.eq(request_pending & ~request_counter_ce) # Note: Store only 1 IP/MAC couple, can be improved with a real # table in the future to improve performance when packets are @@ -196,7 +211,7 @@ class LiteEthARPTable(Module): NextState("SEND_REPLY") ).Elif(sink.stb & sink.reply & request_pending, NextState("UPDATE_TABLE"), - ).Elif(request_counter.value == max_requests-1, + ).Elif(request_counter == max_requests-1, NextState("PRESENT_RESPONSE") ).Elif(request.stb | (request_pending & request_timer.done), NextState("CHECK_TABLE") @@ -250,17 +265,17 @@ class LiteEthARPTable(Module): source.request.eq(1), source.ip_address.eq(request_ip_address), If(source.ack, - request_counter.reset.eq(request.stb), - request_counter.ce.eq(1), + request_counter_reset.eq(request.stb), + request_counter_ce.eq(1), request_pending_set.eq(1), request.ack.eq(1), NextState("IDLE") ) ) self.comb += [ - If(request_counter == max_requests-1, + If(request_counter == max_requests - 1, response.failed.eq(1), - request_counter.reset.eq(1), + request_counter_reset.eq(1), request_pending_clr.eq(1) ), response.mac_address.eq(cached_mac_address) diff --git a/liteeth/core/ip.py b/liteeth/core/ip.py index 6e51833..13ca436 100644 --- a/liteeth/core/ip.py +++ b/liteeth/core/ip.py @@ -69,10 +69,13 @@ class LiteEthIPV4Checksum(Module): if not skip_checksum: n_cycles += 1 - self.submodules.counter = counter = Counter(max=n_cycles+1) + counter = Signal(max=n_cycles+1) + counter_ce = Signal() + self.sync += If(counter_ce, counter.eq(counter + 1)) + self.comb += [ - counter.ce.eq(~self.done), - self.done.eq(counter.value == n_cycles) + counter_ce.eq(~self.done), + self.done.eq(counter == n_cycles) ] # ip tx diff --git a/liteeth/frontend/etherbone.py b/liteeth/frontend/etherbone.py index 9645609..9193a1f 100644 --- a/liteeth/frontend/etherbone.py +++ b/liteeth/frontend/etherbone.py @@ -200,12 +200,20 @@ class LiteEthEtherboneRecordReceiver(Module): base_addr_update = Signal() self.sync += If(base_addr_update, base_addr.eq(fifo.source.data)) - self.submodules.counter = counter = Counter(max=512) + counter = Signal(max=512) + counter_reset = Signal() + counter_ce = Signal() + self.sync += \ + If(counter_reset, + counter.eq(0) + ).Elif(counter_ce, + counter.eq(counter + 1) + ) self.submodules.fsm = fsm = FSM(reset_state="IDLE") fsm.act("IDLE", fifo.source.ack.eq(1), - counter.reset.eq(1), + counter_reset.eq(1), If(fifo.source.stb & fifo.source.sop, base_addr_update.eq(1), If(fifo.source.wcount, @@ -217,16 +225,16 @@ class LiteEthEtherboneRecordReceiver(Module): ) fsm.act("RECEIVE_WRITES", source.stb.eq(fifo.source.stb), - source.sop.eq(counter.value == 0), - source.eop.eq(counter.value == fifo.source.wcount-1), + source.sop.eq(counter == 0), + source.eop.eq(counter == fifo.source.wcount-1), source.count.eq(fifo.source.wcount), source.be.eq(fifo.source.byte_enable), - source.addr.eq(base_addr[2:] + counter.value), + source.addr.eq(base_addr[2:] + counter), source.we.eq(1), source.data.eq(fifo.source.data), fifo.source.ack.eq(source.ack), If(source.stb & source.ack, - counter.ce.eq(1), + counter_ce.eq(1), If(source.eop, If(fifo.source.rcount, NextState("RECEIVE_BASE_RET_ADDR") @@ -237,7 +245,7 @@ class LiteEthEtherboneRecordReceiver(Module): ) ) fsm.act("RECEIVE_BASE_RET_ADDR", - counter.reset.eq(1), + counter_reset.eq(1), If(fifo.source.stb & fifo.source.sop, base_addr_update.eq(1), NextState("RECEIVE_READS") @@ -245,14 +253,14 @@ class LiteEthEtherboneRecordReceiver(Module): ) fsm.act("RECEIVE_READS", source.stb.eq(fifo.source.stb), - source.sop.eq(counter.value == 0), - source.eop.eq(counter.value == fifo.source.rcount-1), + source.sop.eq(counter == 0), + source.eop.eq(counter == fifo.source.rcount-1), source.count.eq(fifo.source.rcount), source.base_addr.eq(base_addr), source.addr.eq(fifo.source.data[2:]), fifo.source.ack.eq(source.ack), If(source.stb & source.ack, - counter.ce.eq(1), + counter_ce.eq(1), If(source.eop, NextState("IDLE") ) diff --git a/liteeth/frontend/tty.py b/liteeth/frontend/tty.py index 72ce89a..02ff844 100644 --- a/liteeth/frontend/tty.py +++ b/liteeth/frontend/tty.py @@ -25,23 +25,31 @@ class LiteEthTTYTX(Module): level_update = Signal() self.sync += If(level_update, level.eq(fifo.level)) - self.submodules.counter = counter = Counter(max=fifo_depth) + counter = Signal(max=fifo_depth) + counter_reset = Signal() + counter_ce = Signal() + self.sync += \ + If(counter_reset, + counter.eq(0) + ).Elif(counter_ce, + counter.eq(counter + 1) + ) self.submodules.fsm = fsm = FSM(reset_state="IDLE") fsm.act("IDLE", If(fifo.source.stb, level_update.eq(1), - counter.reset.eq(1), + counter_reset.eq(1), NextState("SEND") ) ) fsm.act("SEND", source.stb.eq(fifo.source.stb), - source.sop.eq(counter.value == 0), + source.sop.eq(counter == 0), If(level == 0, source.eop.eq(1), ).Else( - source.eop.eq(counter.value == (level-1)), + source.eop.eq(counter == (level-1)), ), source.src_port.eq(udp_port), source.dst_port.eq(udp_port), @@ -54,7 +62,7 @@ class LiteEthTTYTX(Module): source.data.eq(fifo.source.data), fifo.source.ack.eq(source.ack), If(source.stb & source.ack, - counter.ce.eq(1), + counter_ce.eq(1), If(source.eop, NextState("IDLE") ) diff --git a/liteeth/phy/mii.py b/liteeth/phy/mii.py index a140c18..b8189b9 100644 --- a/liteeth/phy/mii.py +++ b/liteeth/phy/mii.py @@ -84,10 +84,12 @@ class LiteEthPHYMIICRG(Module, AutoCSR): if with_hw_init_reset: reset = Signal() counter_done = Signal() - self.submodules.counter = counter = Counter(max=512) + counter = Signal(max=512) + counter_ce = Signal() + self.sync += If(counter_ce, counter.eq(counter + 1)) self.comb += [ - counter_done.eq(counter.value == 256), - counter.ce.eq(~counter_done), + counter_done.eq(counter == 256), + counter_ce.eq(~counter_done), reset.eq(~counter_done | self._reset.storage) ] else: diff --git a/liteeth/phy/rmii.py b/liteeth/phy/rmii.py index d3590ce..ffe9fbb 100644 --- a/liteeth/phy/rmii.py +++ b/liteeth/phy/rmii.py @@ -82,10 +82,12 @@ class LiteEthPHYMIICRG(Module, AutoCSR): if with_hw_init_reset: reset = Signal() counter_done = Signal() - self.submodules.counter = counter = Counter(max=512) + counter = Signal(max=512) + counter_ce = Signal() + self.sync += If(counter_ce, counter.eq(counter + 1)) self.comb += [ - counter_done.eq(counter.value == 256), - counter.ce.eq(~counter_done), + counter_done.eq(counter == 256), + counter_ce.eq(~counter_done), reset.eq(~counter_done | self._reset.storage) ] else: diff --git a/liteeth/phy/s6rgmii.py b/liteeth/phy/s6rgmii.py index d3d49d6..7432c46 100644 --- a/liteeth/phy/s6rgmii.py +++ b/liteeth/phy/s6rgmii.py @@ -135,10 +135,12 @@ class LiteEthPHYRGMIICRG(Module, AutoCSR): if with_hw_init_reset: reset = Signal() counter_done = Signal() - self.submodules.counter = counter = Counter(max=512) + counter = Signal(max=512) + counter_ce = Signal() + self.sync += If(counter_ce, counter.eq(counter + 1)) self.comb += [ - counter_done.eq(counter.value == 256), - counter.ce.eq(~counter_done), + counter_done.eq(counter == 256), + counter_ce.eq(~counter_done), reset.eq(~counter_done | self._reset.storage) ] else: