From 4cd0a99187677553078fcefbf78eb15863b6ed61 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 23 Mar 2022 08:44:52 +0100 Subject: [PATCH] phy/1000basex: Add crg_reset CSR for consistency with other PHYs. --- liteeth/phy/a7_1000basex.py | 9 ++++++--- liteeth/phy/k7_1000basex.py | 9 ++++++--- liteeth/phy/ku_1000basex.py | 9 ++++++--- liteeth/phy/usp_1000basex.py | 9 ++++++--- 4 files changed, 24 insertions(+), 12 deletions(-) diff --git a/liteeth/phy/a7_1000basex.py b/liteeth/phy/a7_1000basex.py index 764baac..71729cf 100644 --- a/liteeth/phy/a7_1000basex.py +++ b/liteeth/phy/a7_1000basex.py @@ -9,6 +9,7 @@ from migen import * from migen.genlib.resetsync import AsyncResetSynchronizer from migen.genlib.cdc import PulseSynchronizer +from liteeth.common import * from liteeth.phy.a7_gtp import * from liteeth.phy.pcs_1000basex import * @@ -43,7 +44,7 @@ class Gearbox(Module): ] -class A7_1000BASEX(Module): +class A7_1000BASEX(Module, AutoCSR): dw = 8 tx_clk_freq = 125e6 rx_clk_freq = 125e6 @@ -64,6 +65,8 @@ class A7_1000BASEX(Module): self.txoutclk = Signal() self.rxoutclk = Signal() + self.crg_reset = CSRStorage() + # # # # GTP transceiver @@ -782,7 +785,7 @@ class A7_1000BASEX(Module): self.comb += [ qpll_channel.reset.eq(tx_init.qpll_reset), tx_init.qpll_lock.eq(qpll_channel.lock), - tx_reset.eq(tx_init.tx_reset) + tx_reset.eq(tx_init.tx_reset | self.crg_reset.storage) ] self.sync += tx_mmcm_reset.eq(~qpll_channel.lock) tx_mmcm_reset.attr.add("no_retiming") @@ -791,7 +794,7 @@ class A7_1000BASEX(Module): self.submodules += rx_init self.comb += [ rx_init.enable.eq(tx_init.done), - rx_reset.eq(rx_init.rx_reset), + rx_reset.eq(rx_init.rx_reset | self.crg_reset.storage), rx_init.rx_pma_reset_done.eq(rx_pma_reset_done), drpaddr.eq(rx_init.drpaddr), diff --git a/liteeth/phy/k7_1000basex.py b/liteeth/phy/k7_1000basex.py index 36084fc..7acabcc 100644 --- a/liteeth/phy/k7_1000basex.py +++ b/liteeth/phy/k7_1000basex.py @@ -10,6 +10,7 @@ from migen.genlib.cdc import PulseSynchronizer from liteiclink.transceiver.gtx_7series import GTXChannelPLL, GTXTXInit, GTXRXInit +from liteeth.common import * from liteeth.phy.pcs_1000basex import * @@ -44,7 +45,7 @@ class Gearbox(Module): # Configured for 200MHz transceiver reference clock -class K7_1000BASEX(Module): +class K7_1000BASEX(Module, AutoCSR): dw = 8 tx_clk_freq = 125e6 rx_clk_freq = 125e6 @@ -65,6 +66,8 @@ class K7_1000BASEX(Module): self.txoutclk = Signal() self.rxoutclk = Signal() + self.crg_reset = CSRStorage() + # # # if isinstance(refclk_or_clk_pads, Signal): @@ -810,7 +813,7 @@ class K7_1000BASEX(Module): self.comb += [ pll.reset.eq(tx_init.pllreset), tx_init.plllock.eq(pll.lock), - tx_reset.eq(tx_init.gtXxreset) + tx_reset.eq(tx_init.gtXxreset | self.crg_reset.storage) ] self.sync += tx_mmcm_reset.eq(~pll.lock) tx_mmcm_reset.attr.add("no_retiming") @@ -820,7 +823,7 @@ class K7_1000BASEX(Module): self.submodules += rx_init self.comb += [ rx_init.reset.eq(~tx_init.done), - rx_reset.eq(rx_init.gtXxreset) + rx_reset.eq(rx_init.gtXxreset | self.crg_reset.storage) ] ps_restart = PulseSynchronizer("eth_tx", "sys") self.submodules += ps_restart diff --git a/liteeth/phy/ku_1000basex.py b/liteeth/phy/ku_1000basex.py index 1fdee52..2f7baf7 100644 --- a/liteeth/phy/ku_1000basex.py +++ b/liteeth/phy/ku_1000basex.py @@ -9,6 +9,7 @@ from migen import * from migen.genlib.resetsync import AsyncResetSynchronizer from migen.genlib.cdc import PulseSynchronizer +from liteeth.common import * from liteeth.phy.pcs_1000basex import * @@ -43,7 +44,7 @@ class Gearbox(Module): # Configured for 200MHz transceiver reference clock -class KU_1000BASEX(Module): +class KU_1000BASEX(Module, AutoCSR): dw = 8 tx_clk_freq = 125e6 rx_clk_freq = 125e6 @@ -64,6 +65,8 @@ class KU_1000BASEX(Module): self.txoutclk = Signal() self.rxoutclk = Signal() + self.crg_reset = CSRStorage() + # # # if isinstance(refclk_or_clk_pads, Signal): @@ -861,8 +864,8 @@ class KU_1000BASEX(Module): ) ] self.comb += [ - tx_reset.eq(pll_reset | ~pll_locked), - rx_reset.eq(pll_reset | ~pll_locked | pcs.restart) + tx_reset.eq(pll_reset | ~pll_locked | self.crg_reset.storage), + rx_reset.eq(pll_reset | ~pll_locked | pcs.restart | self.crg_reset.storage) ] # Gearbox and PCS connection diff --git a/liteeth/phy/usp_1000basex.py b/liteeth/phy/usp_1000basex.py index ebb8b08..e2e33df 100644 --- a/liteeth/phy/usp_1000basex.py +++ b/liteeth/phy/usp_1000basex.py @@ -11,6 +11,7 @@ from migen import * from migen.genlib.resetsync import AsyncResetSynchronizer from migen.genlib.cdc import PulseSynchronizer +from liteeth.common import * from liteeth.phy.pcs_1000basex import * @@ -45,7 +46,7 @@ class Gearbox(Module): # Configured for 200MHz transceiver reference clock -class USP_1000BASEX(Module): +class USP_1000BASEX(Module, AutoCSR): dw = 8 tx_clk_freq = 125e6 rx_clk_freq = 125e6 @@ -66,6 +67,8 @@ class USP_1000BASEX(Module): self.txoutclk = Signal() self.rxoutclk = Signal() + self.crg_reset = CSRStorage() + # # # if isinstance(refclk_or_clk_pads, Signal): @@ -966,8 +969,8 @@ class USP_1000BASEX(Module): ) ] self.comb += [ - tx_reset.eq(pll_reset | ~pll_locked), - rx_reset.eq(pll_reset | ~pll_locked | pcs.restart) + tx_reset.eq(pll_reset | ~pll_locked | self.crg_reset.storage), + rx_reset.eq(pll_reset | ~pll_locked | pcs.restart | self.crg_reset.storage) ] # Gearbox and PCS connection