From 4d9e74f10a3fe7bf71ba9bde50f49689c6458dc5 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Sat, 28 Sep 2019 22:16:07 +0200 Subject: [PATCH] phy/usrgmii: cleanup (style, indent) --- liteeth/phy/usrgmii.py | 168 ++++++++++++++++++++--------------------- 1 file changed, 83 insertions(+), 85 deletions(-) diff --git a/liteeth/phy/usrgmii.py b/liteeth/phy/usrgmii.py index 08e04b0..585e0c9 100644 --- a/liteeth/phy/usrgmii.py +++ b/liteeth/phy/usrgmii.py @@ -2,10 +2,10 @@ # License: BSD # RGMII PHY for Ultrascale Xilinx FPGAs -# Tested on hardware (HTG-940) with liteeth: ad187d litex: 41fe7c + +from migen.genlib.resetsync import AsyncResetSynchronizer from liteeth.common import * -from migen.genlib.resetsync import AsyncResetSynchronizer from liteeth.phy.common import * @@ -20,22 +20,26 @@ class LiteEthPHYRGMIITX(Module): self.specials += [ Instance("ODDRE1", - i_C=ClockSignal("eth_tx"), - i_SR=0, - i_D1=sink.valid, - i_D2=sink.valid, - o_Q=tx_ctl_obuf), - Instance("OBUF", i_I=tx_ctl_obuf, o_O=pads.tx_ctl) + i_C=ClockSignal("eth_tx"), + i_SR=0, + i_D1=sink.valid, + i_D2=sink.valid, + o_Q=tx_ctl_obuf), + Instance("OBUF", + i_I=tx_ctl_obuf, + o_O=pads.tx_ctl) ] for i in range(4): self.specials += [ Instance("ODDRE1", - i_C=ClockSignal("eth_tx"), - i_SR=0, - i_D1=sink.data[i], - i_D2=sink.data[4 + i], - o_Q=tx_data_obuf[i]), - Instance("OBUF", i_I=tx_data_obuf[i], o_O=pads.tx_data[i]) + i_C=ClockSignal("eth_tx"), + i_SR=0, + i_D1=sink.data[i], + i_D2=sink.data[4 + i], + o_Q=tx_data_obuf[i]), + Instance("OBUF", + i_I=tx_data_obuf[i], + o_O=pads.tx_data[i]) ] self.comb += sink.ready.eq(1) @@ -55,71 +59,67 @@ class LiteEthPHYRGMIIRX(Module): self.specials += [ Instance("IBUF", i_I=pads.rx_ctl, o_O=rx_ctl_ibuf), - # Using 0 delay throug the IDELAYE3 element. - # DELAY_TYPE is COUNT, and _FORMAT is FIXED Instance("IDELAYE3", - # Using the following defaults in comments. - # p_DELAY_SRC="IDATAIN", - # p_CASCADE="NONE", - # p_DELAY_TYPE="FIXED", - # p_DELAY_VALUE=0, - # p_REFCLK_FREQUENCY=300.0, # default DELAY_FORMAT=COUNT - p_DELAY_FORMAT="COUNT", - # p_UPDATE_MODE="ASYNC", # We never update - i_CASC_IN=0, - i_CASC_RETURN=0, - i_CE=0, - i_CLK=0, - i_INC=0, - i_LOAD=0, - i_CNTVALUEIN=0, - i_IDATAIN=rx_ctl_ibuf, - i_RST=0, - i_EN_VTC=0, - o_DATAOUT=rx_ctl_idelay), + p_DELAY_SRC="IDATAIN", + p_CASCADE="NONE", + p_DELAY_TYPE="FIXED", + p_DELAY_VALUE=0, + p_REFCLK_FREQUENCY=300.0, + p_DELAY_FORMAT="COUNT", + p_UPDATE_MODE="ASYNC", + i_CASC_IN=0, + i_CASC_RETURN=0, + i_CE=0, + i_CLK=0, + i_INC=0, + i_LOAD=0, + i_CNTVALUEIN=0, + i_IDATAIN=rx_ctl_ibuf, + i_RST=0, + i_EN_VTC=0, + o_DATAOUT=rx_ctl_idelay), Instance("IDDRE1", - p_DDR_CLK_EDGE="SAME_EDGE_PIPELINED", - p_IS_C_INVERTED=0, - p_IS_CB_INVERTED=1, - i_C=ClockSignal("eth_rx"), - i_CB=ClockSignal("eth_rx"), - i_R=0, - i_D=rx_ctl_idelay, - o_Q1=rx_ctl, # o_Q2=, - ) + p_DDR_CLK_EDGE="SAME_EDGE_PIPELINED", + p_IS_C_INVERTED=0, + p_IS_CB_INVERTED=1, + i_C=ClockSignal("eth_rx"), + i_CB=ClockSignal("eth_rx"), + i_R=0, + i_D=rx_ctl_idelay, + o_Q1=rx_ctl, + o_Q2=Signal()) ] for i in range(4): self.specials += [ - Instance( - "IBUF", i_I=pads.rx_data[i], o_O=rx_data_ibuf[i]), + Instance("IBUF", i_I=pads.rx_data[i], o_O=rx_data_ibuf[i]), Instance("IDELAYE3", - # p_DELAY_SRC="IDATAIN", - # p_CASCADE="NONE", - # p_DELAY_TYPE="FIXED", - # p_DELAY_VALUE=0, - # p_UPDATE_MODE='ASYNC", - p_DELAY_FORMAT="COUNT", - i_CASC_IN=0, - i_CASC_RETURN=0, - i_CE=0, - i_CLK=0, - i_INC=0, - i_LOAD=0, - i_CNTVALUEIN=0, - i_IDATAIN=rx_data_ibuf[i], - i_RST=0, - i_EN_VTC=0, - o_DATAOUT=rx_data_idelay[i]), + p_DELAY_SRC="IDATAIN", + p_CASCADE="NONE", + p_DELAY_TYPE="FIXED", + p_DELAY_VALUE=0, + p_UPDATE_MODE="ASYNC", + p_DELAY_FORMAT="COUNT", + i_CASC_IN=0, + i_CASC_RETURN=0, + i_CE=0, + i_CLK=0, + i_INC=0, + i_LOAD=0, + i_CNTVALUEIN=0, + i_IDATAIN=rx_data_ibuf[i], + i_RST=0, + i_EN_VTC=0, + o_DATAOUT=rx_data_idelay[i]), Instance("IDDRE1", - p_DDR_CLK_EDGE="SAME_EDGE_PIPELINED", - p_IS_C_INVERTED=0, - p_IS_CB_INVERTED=1, - i_C=ClockSignal("eth_rx"), - i_CB=ClockSignal("eth_rx"), - i_R=0, - i_D=rx_data_idelay[i], - o_Q1=rx_data[i], - o_Q2=rx_data[i + 4], ) + p_DDR_CLK_EDGE="SAME_EDGE_PIPELINED", + p_IS_C_INVERTED=0, + p_IS_CB_INVERTED=1, + i_C=ClockSignal("eth_rx"), + i_CB=ClockSignal("eth_rx"), + i_R=0, + i_D=rx_data_idelay[i], + o_Q1=rx_data[i], + o_Q2=rx_data[i + 4]) ] rx_ctl_d = Signal() @@ -144,9 +144,12 @@ class LiteEthPHYRGMIICRG(Module, AutoCSR): # RX eth_rx_clk_ibuf = Signal() self.specials += [ - Instance( - "IBUF", i_I=clock_pads.rx, o_O=eth_rx_clk_ibuf), Instance( - "BUFG", i_I=eth_rx_clk_ibuf, o_O=self.cd_eth_rx.clk) + Instance("IBUF", + i_I=clock_pads.rx, + o_O=eth_rx_clk_ibuf), + Instance("BUFG", + i_I=eth_rx_clk_ibuf, + o_O=self.cd_eth_rx.clk) ] # TX @@ -156,8 +159,7 @@ class LiteEthPHYRGMIICRG(Module, AutoCSR): pll_clk_tx90 = Signal() eth_tx_clk_obuf = Signal() self.specials += [ - Instance( - "PLLE2_BASE", + Instance("PLLE2_BASE", p_STARTUP_WAIT="FALSE", o_LOCKED=pll_locked, @@ -179,19 +181,15 @@ class LiteEthPHYRGMIICRG(Module, AutoCSR): p_CLKOUT1_DIVIDE=8, p_CLKOUT1_PHASE=90.0, o_CLKOUT1=pll_clk_tx90), - Instance( - "BUFG", i_I=pll_clk_tx, o_O=self.cd_eth_tx.clk), - Instance( - "BUFG", i_I=pll_clk_tx90, o_O=self.cd_eth_tx90.clk), - Instance( - "ODDRE1", + Instance("BUFG", i_I=pll_clk_tx, o_O=self.cd_eth_tx.clk), + Instance("BUFG", i_I=pll_clk_tx90, o_O=self.cd_eth_tx90.clk), + Instance("ODDRE1", i_C=ClockSignal("eth_tx90"), i_SR=0, i_D1=1, i_D2=0, o_Q=eth_tx_clk_obuf), - Instance( - "OBUF", i_I=eth_tx_clk_obuf, o_O=clock_pads.tx) + Instance("OBUF", i_I=eth_tx_clk_obuf, o_O=clock_pads.tx) ] # Reset