From 50ad88cc855a1f19d664ae4ee6d7ed24ac118cbc Mon Sep 17 00:00:00 2001 From: Jiaxun Yang Date: Mon, 16 Dec 2024 15:50:58 +0000 Subject: [PATCH] phy/usp_gth/gty_1000basex: Set proper CPLLREFCLKSEL for refclk_from_fabric As per Xilinx UG578 CPLLREFCLKSEL needs to be set to 111 when using GTGREFCLK as clock source. Signed-off-by: Jiaxun Yang --- liteeth/phy/usp_gth_1000basex.py | 2 +- liteeth/phy/usp_gty_1000basex.py | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/liteeth/phy/usp_gth_1000basex.py b/liteeth/phy/usp_gth_1000basex.py index 1c2c1ed..0a78087 100644 --- a/liteeth/phy/usp_gth_1000basex.py +++ b/liteeth/phy/usp_gth_1000basex.py @@ -565,7 +565,7 @@ class USP_GTH_1000BASEX(LiteXModule): i_CPLLLOCKDETCLK = 0b0, i_CPLLLOCKEN = 0b1, i_CPLLPD = pll_reset, - i_CPLLREFCLKSEL = 0b001, + i_CPLLREFCLKSEL = 0b111 if refclk_from_fabric else 0b001, i_CPLLRESET = 0b0, i_DMONFIFORESET = 0b0, i_DMONITORCLK = 0b0, diff --git a/liteeth/phy/usp_gty_1000basex.py b/liteeth/phy/usp_gty_1000basex.py index 31c1bac..cfaef3f 100644 --- a/liteeth/phy/usp_gty_1000basex.py +++ b/liteeth/phy/usp_gty_1000basex.py @@ -581,7 +581,7 @@ class USP_GTY_1000BASEX(LiteXModule): i_CPLLLOCKDETCLK = 0b0, i_CPLLLOCKEN = 0b1, i_CPLLPD = pll_reset, - i_CPLLREFCLKSEL = 0b001, + i_CPLLREFCLKSEL = 0b111 if refclk_from_fabric else 0b001, i_CPLLRESET = 0b0, i_DMONFIFORESET = 0b0, i_DMONITORCLK = 0b0,