diff --git a/example_designs/targets/base.py b/example_designs/targets/base.py index c591fe8..eab3a9e 100644 --- a/example_designs/targets/base.py +++ b/example_designs/targets/base.py @@ -81,33 +81,28 @@ class BaseSoCDevel(BaseSoC): debug = ( # MAC interface self.core.mac.core.sink.stb, - self.core.mac.core.sink.sop, self.core.mac.core.sink.eop, self.core.mac.core.sink.ack, self.core.mac.core.sink.data, self.core.mac.core.source.stb, - self.core.mac.core.source.sop, self.core.mac.core.source.eop, self.core.mac.core.source.ack, self.core.mac.core.source.data, # ICMP interface self.core.icmp.echo.sink.stb, - self.core.icmp.echo.sink.sop, self.core.icmp.echo.sink.eop, self.core.icmp.echo.sink.ack, self.core.icmp.echo.sink.data, self.core.icmp.echo.source.stb, - self.core.icmp.echo.source.sop, self.core.icmp.echo.source.eop, self.core.icmp.echo.source.ack, self.core.icmp.echo.source.data, # IP interface self.core.ip.crossbar.master.sink.stb, - self.core.ip.crossbar.master.sink.sop, self.core.ip.crossbar.master.sink.eop, self.core.ip.crossbar.master.sink.ack, self.core.ip.crossbar.master.sink.data, diff --git a/example_designs/targets/core.py b/example_designs/targets/core.py index a8b89e5..7a2610a 100644 --- a/example_designs/targets/core.py +++ b/example_designs/targets/core.py @@ -112,7 +112,6 @@ _io = [ # UDP ("udp_sink", 0, Subsignal("stb", Pins(1)), - Subsignal("sop", Pins(1)), Subsignal("eop", Pins(1)), Subsignal("ack", Pins(1)), # param @@ -127,7 +126,6 @@ _io = [ ("udp_source", 0, Subsignal("stb", Pins(1)), - Subsignal("sop", Pins(1)), Subsignal("eop", Pins(1)), Subsignal("ack", Pins(1)), # param @@ -224,7 +222,6 @@ class UDPCore(PHYCore): self.comb += [ # control udp_port.sink.stb.eq(udp_sink.stb), - udp_port.sink.sop.eq(udp_sink.sop), udp_port.sink.eop.eq(udp_sink.eop), udp_sink.ack.eq(udp_port.sink.ack), @@ -242,7 +239,6 @@ class UDPCore(PHYCore): self.comb += [ # control udp_source.stb.eq(udp_port.source.stb), - udp_source.sop.eq(udp_port.source.sop), udp_source.eop.eq(udp_port.source.eop), udp_port.source.ack.eq(udp_source.ack), diff --git a/example_designs/targets/etherbone.py b/example_designs/targets/etherbone.py index 7df6990..886d11d 100644 --- a/example_designs/targets/etherbone.py +++ b/example_designs/targets/etherbone.py @@ -26,7 +26,6 @@ class EtherboneSoCDevel(EtherboneSoC): debug = ( # mmap stream from HOST self.etherbone.master.sink.stb, - self.etherbone.master.sink.sop, self.etherbone.master.sink.eop, self.etherbone.master.sink.ack, self.etherbone.master.sink.we, @@ -38,7 +37,6 @@ class EtherboneSoCDevel(EtherboneSoC): # mmap stream to HOST self.etherbone.master.source.stb, - self.etherbone.master.source.sop, self.etherbone.master.source.eop, self.etherbone.master.source.ack, self.etherbone.master.source.we, diff --git a/example_designs/targets/udp.py b/example_designs/targets/udp.py index c64b7fb..62aa311 100644 --- a/example_designs/targets/udp.py +++ b/example_designs/targets/udp.py @@ -38,25 +38,21 @@ class UDPSoCDevel(UDPSoC): UDPSoC.__init__(self, platform) debug = ( self.loopback_8.sink.stb, - self.loopback_8.sink.sop, self.loopback_8.sink.eop, self.loopback_8.sink.ack, self.loopback_8.sink.data, self.loopback_8.source.stb, - self.loopback_8.source.sop, self.loopback_8.source.eop, self.loopback_8.source.ack, self.loopback_8.source.data, self.loopback_32.sink.stb, - self.loopback_32.sink.sop, self.loopback_32.sink.eop, self.loopback_32.sink.ack, self.loopback_32.sink.data, self.loopback_32.source.stb, - self.loopback_32.source.sop, self.loopback_32.source.eop, self.loopback_32.source.ack, self.loopback_32.source.data diff --git a/liteeth/core/arp.py b/liteeth/core/arp.py index d59bcb4..22282f1 100644 --- a/liteeth/core/arp.py +++ b/liteeth/core/arp.py @@ -50,7 +50,6 @@ class LiteEthARPTX(Module): ) ) self.comb += [ - packetizer.sink.sop.eq(counter == 0), packetizer.sink.eop.eq(counter == max(arp_header.length, eth_min_len)-1), packetizer.sink.hwtype.eq(arp_hwtype_ethernet), packetizer.sink.proto.eq(arp_proto_ip), @@ -107,7 +106,7 @@ class LiteEthARPRX(Module): self.submodules.fsm = fsm = FSM(reset_state="IDLE") fsm.act("IDLE", depacketizer.source.ack.eq(1), - If(depacketizer.source.stb & depacketizer.source.sop, + If(depacketizer.source.stb, depacketizer.source.ack.eq(0), NextState("CHECK") ) diff --git a/liteeth/core/icmp.py b/liteeth/core/icmp.py index 4215275..2590eeb 100644 --- a/liteeth/core/icmp.py +++ b/liteeth/core/icmp.py @@ -23,7 +23,6 @@ class LiteEthICMPTX(Module): self.submodules.packetizer = packetizer = LiteEthICMPPacketizer() self.comb += [ packetizer.sink.stb.eq(sink.stb), - packetizer.sink.sop.eq(sink.sop), packetizer.sink.eop.eq(sink.eop), sink.ack.eq(packetizer.sink.ack), packetizer.sink.msgtype.eq(sink.msgtype), @@ -36,7 +35,7 @@ class LiteEthICMPTX(Module): self.submodules.fsm = fsm = FSM(reset_state="IDLE") fsm.act("IDLE", packetizer.source.ack.eq(1), - If(packetizer.source.stb & packetizer.source.sop, + If(packetizer.source.stb, packetizer.source.ack.eq(0), NextState("SEND") ) @@ -74,7 +73,7 @@ class LiteEthICMPRX(Module): self.submodules.fsm = fsm = FSM(reset_state="IDLE") fsm.act("IDLE", depacketizer.source.ack.eq(1), - If(depacketizer.source.stb & depacketizer.source.sop, + If(depacketizer.source.stb, depacketizer.source.ack.eq(0), NextState("CHECK") ) @@ -92,7 +91,6 @@ class LiteEthICMPRX(Module): ) ) self.comb += [ - source.sop.eq(depacketizer.source.sop), source.eop.eq(depacketizer.source.eop), source.msgtype.eq(depacketizer.source.msgtype), source.code.eq(depacketizer.source.code), diff --git a/liteeth/core/ip.py b/liteeth/core/ip.py index ff12e51..aed4aad 100644 --- a/liteeth/core/ip.py +++ b/liteeth/core/ip.py @@ -98,14 +98,13 @@ class LiteEthIPTX(Module): self.submodules.checksum = checksum = LiteEthIPV4Checksum(skip_checksum=True) self.comb += [ - checksum.ce.eq(sink.stb & sink.sop), + checksum.ce.eq(sink.stb), checksum.reset.eq(source.stb & source.eop & source.ack) ] self.submodules.packetizer = packetizer = LiteEthIPV4Packetizer() self.comb += [ packetizer.sink.stb.eq(sink.stb & checksum.done), - packetizer.sink.sop.eq(sink.sop), packetizer.sink.eop.eq(sink.eop), sink.ack.eq(packetizer.sink.ack & checksum.done), packetizer.sink.target_ip.eq(sink.ip_address), @@ -126,7 +125,7 @@ class LiteEthIPTX(Module): self.submodules.fsm = fsm = FSM(reset_state="IDLE") fsm.act("IDLE", packetizer.source.ack.eq(1), - If(packetizer.source.stb & packetizer.source.sop, + If(packetizer.source.stb, packetizer.source.ack.eq(0), NextState("SEND_MAC_ADDRESS_REQUEST") ) @@ -194,14 +193,14 @@ class LiteEthIPRX(Module): self.submodules.checksum = checksum = LiteEthIPV4Checksum(skip_checksum=False) self.comb += [ checksum.header.eq(depacketizer.header), - checksum.reset.eq(~(depacketizer.source.stb & depacketizer.source.sop)), + checksum.reset.eq(~(depacketizer.source.stb)), checksum.ce.eq(1) ] self.submodules.fsm = fsm = FSM(reset_state="IDLE") fsm.act("IDLE", depacketizer.source.ack.eq(1), - If(depacketizer.source.stb & depacketizer.source.sop, + If(depacketizer.source.stb, depacketizer.source.ack.eq(0), NextState("CHECK") ) @@ -225,7 +224,6 @@ class LiteEthIPRX(Module): ) ) self.comb += [ - source.sop.eq(depacketizer.source.sop), source.eop.eq(depacketizer.source.eop), source.length.eq(depacketizer.source.total_length - (0x5*4)), source.protocol.eq(depacketizer.source.protocol), diff --git a/liteeth/core/mac/crc.py b/liteeth/core/mac/crc.py index 43bd888..3e404a0 100644 --- a/liteeth/core/mac/crc.py +++ b/liteeth/core/mac/crc.py @@ -151,7 +151,7 @@ class LiteEthMACCRCInserter(Module): fsm.act("IDLE", crc.reset.eq(1), sink.ack.eq(1), - If(sink.stb & sink.sop, + If(sink.stb, sink.ack.eq(0), NextState("COPY"), ) @@ -242,12 +242,11 @@ class LiteEthMACCRCChecker(Module): fifo_in.eq(sink.stb & (~fifo_full | fifo_out)), fifo_out.eq(source.stb & source.ack), - sink.connect(fifo.sink, leave_out=set(["stb", "ack"])), + sink.connect(fifo.sink), fifo.sink.stb.eq(fifo_in), self.sink.ack.eq(fifo_in), source.stb.eq(sink.stb & fifo_full), - source.sop.eq(fifo.source.sop), source.eop.eq(sink.eop), fifo.source.ack.eq(fifo_out), source.payload.eq(fifo.source.payload), @@ -262,7 +261,7 @@ class LiteEthMACCRCChecker(Module): ) self.comb += crc.data.eq(sink.data) fsm.act("IDLE", - If(sink.stb & sink.sop & sink.ack, + If(sink.stb & sink.ack, crc.ce.eq(1), NextState("COPY") ) diff --git a/liteeth/core/mac/last_be.py b/liteeth/core/mac/last_be.py index eb6bffd..24d9ba7 100644 --- a/liteeth/core/mac/last_be.py +++ b/liteeth/core/mac/last_be.py @@ -8,18 +8,17 @@ class LiteEthMACTXLastBE(Module): # # # - ongoing = Signal() + ongoing = Signal(reset=1) self.sync += \ If(sink.stb & sink.ack, - If(sink.sop, + If(sink.eop, ongoing.eq(1) ).Elif(sink.last_be, ongoing.eq(0) ) ) self.comb += [ - source.stb.eq(sink.stb & (sink.sop | ongoing)), - source.sop.eq(sink.sop), + source.stb.eq(sink.stb & ongoing), source.eop.eq(sink.last_be), source.data.eq(sink.data), sink.ack.eq(source.ack) @@ -34,10 +33,6 @@ class LiteEthMACRXLastBE(Module): # # # self.comb += [ - source.stb.eq(sink.stb), - source.sop.eq(sink.sop), - source.eop.eq(sink.eop), - source.data.eq(sink.data), - source.last_be.eq(sink.eop), - sink.ack.eq(source.ack) + sink.connect(source), + source.last_be.eq(sink.eop) ] diff --git a/liteeth/core/mac/padding.py b/liteeth/core/mac/padding.py index ad02f7c..1b53391 100644 --- a/liteeth/core/mac/padding.py +++ b/liteeth/core/mac/padding.py @@ -16,16 +16,13 @@ class LiteEthMACPaddingInserter(Module): counter_done = Signal() counter_reset = Signal() counter_ce = Signal() - self.sync += If(counter_reset, - counter.eq(1) - ).Elif(counter_ce, - counter.eq(counter + 1) - ) - self.comb += [ - counter_reset.eq(sink.stb & sink.sop & sink.ack), - counter_ce.eq(source.stb & source.ack), - counter_done.eq(counter >= padding_limit), - ] + self.sync += \ + If(counter_reset, + counter.eq(0) + ).Elif(counter_ce, + counter.eq(counter + 1) + ) + self.comb += counter_done.eq(counter >= padding_limit) self.submodules.fsm = fsm = FSM(reset_state="IDLE") fsm.act("IDLE", @@ -36,6 +33,8 @@ class LiteEthMACPaddingInserter(Module): If(~counter_done, source.eop.eq(0), NextState("PADDING") + ).Else( + counter_reset.eq(1) ) ) ) @@ -44,8 +43,10 @@ class LiteEthMACPaddingInserter(Module): source.stb.eq(1), source.eop.eq(counter_done), source.data.eq(0), - If(source.ack, + If(source.stb & source.ack, + counter_ce.eq(1), If(counter_done, + counter_reset.eq(1), NextState("IDLE") ) ) diff --git a/liteeth/core/mac/preamble.py b/liteeth/core/mac/preamble.py index bd75da5..cdeab8b 100644 --- a/liteeth/core/mac/preamble.py +++ b/liteeth/core/mac/preamble.py @@ -28,14 +28,13 @@ class LiteEthMACPreambleInserter(Module): fsm.act("IDLE", self.sink.ack.eq(1), clr_cnt.eq(1), - If(self.sink.stb & self.sink.sop, + If(self.sink.stb, self.sink.ack.eq(0), NextState("INSERT"), ) ) fsm.act("INSERT", self.source.stb.eq(1), - self.source.sop.eq(cnt == 0), chooser(preamble, cnt, self.source.data), If(cnt == cnt_max, If(self.source.ack, NextState("COPY")) @@ -50,7 +49,6 @@ class LiteEthMACPreambleInserter(Module): ] fsm.act("COPY", self.sink.connect(self.source, leave_out=set(["data", "last_be"])), - self.source.sop.eq(0), If(self.sink.stb & self.sink.eop & self.source.ack, NextState("IDLE"), @@ -89,16 +87,6 @@ class LiteEthMACPreambleChecker(Module): discard.eq(1) ) - sop = Signal() - clr_sop = Signal() - set_sop = Signal() - self.sync += \ - If(clr_sop, - sop.eq(0) - ).Elif(set_sop, - sop.eq(1) - ) - ref = Signal(dw) match = Signal() self.comb += [ @@ -113,7 +101,7 @@ class LiteEthMACPreambleChecker(Module): self.sink.ack.eq(1), clr_cnt.eq(1), clr_discard.eq(1), - If(self.sink.stb & self.sink.sop, + If(self.sink.stb, clr_cnt.eq(0), inc_cnt.eq(1), clr_discard.eq(0), @@ -129,7 +117,6 @@ class LiteEthMACPreambleChecker(Module): If(discard | (~match), NextState("IDLE") ).Else( - set_sop.eq(1), NextState("COPY") ) ).Else( @@ -143,9 +130,6 @@ class LiteEthMACPreambleChecker(Module): ] fsm.act("COPY", self.sink.connect(self.source, leave_out=set(["data", "last_be"])), - self.source.sop.eq(sop), - clr_sop.eq(self.source.stb & self.source.ack), - If(self.source.stb & self.source.eop & self.source.ack, NextState("IDLE"), ) diff --git a/liteeth/core/mac/sram.py b/liteeth/core/mac/sram.py index 59fb535..57eca2b 100644 --- a/liteeth/core/mac/sram.py +++ b/liteeth/core/mac/sram.py @@ -63,7 +63,7 @@ class LiteEthMACSRAMWriter(Module, AutoCSR): self.submodules += fsm fsm.act("IDLE", - If(sink.stb & sink.sop, + If(sink.stb, If(fifo.sink.ack, ongoing.eq(1), counter_ce.eq(1), @@ -166,7 +166,6 @@ class LiteEthMACSRAMReader(Module, AutoCSR): # fsm - first = Signal() last = Signal() last_d = Signal() @@ -202,7 +201,6 @@ class LiteEthMACSRAMReader(Module, AutoCSR): ] fsm.act("SEND", source.stb.eq(1), - source.sop.eq(first), source.eop.eq(last), If(source.ack, counter_ce.eq(~last), @@ -215,14 +213,7 @@ class LiteEthMACSRAMReader(Module, AutoCSR): NextState("IDLE") ) - # first/last computation - self.sync += [ - If(fsm.ongoing("IDLE"), - first.eq(1) - ).Elif(source.stb & source.ack, - first.eq(0) - ) - ] + # last computation self.comb += last.eq((counter + 4) >= fifo.source.length) self.sync += last_d.eq(last) diff --git a/liteeth/core/udp.py b/liteeth/core/udp.py index e49409b..8fa99f2 100644 --- a/liteeth/core/udp.py +++ b/liteeth/core/udp.py @@ -74,7 +74,6 @@ class LiteEthUDPTX(Module): self.submodules.packetizer = packetizer = LiteEthUDPPacketizer() self.comb += [ packetizer.sink.stb.eq(sink.stb), - packetizer.sink.sop.eq(sink.sop), packetizer.sink.eop.eq(sink.eop), sink.ack.eq(packetizer.sink.ack), packetizer.sink.src_port.eq(sink.src_port), @@ -87,7 +86,7 @@ class LiteEthUDPTX(Module): self.submodules.fsm = fsm = FSM(reset_state="IDLE") fsm.act("IDLE", packetizer.source.ack.eq(1), - If(packetizer.source.stb & packetizer.source.sop, + If(packetizer.source.stb, packetizer.source.ack.eq(0), NextState("SEND") ) @@ -125,7 +124,7 @@ class LiteEthUDPRX(Module): self.submodules.fsm = fsm = FSM(reset_state="IDLE") fsm.act("IDLE", depacketizer.source.ack.eq(1), - If(depacketizer.source.stb & depacketizer.source.sop, + If(depacketizer.source.stb, depacketizer.source.ack.eq(0), NextState("CHECK") ) @@ -144,7 +143,6 @@ class LiteEthUDPRX(Module): ) ) self.comb += [ - source.sop.eq(depacketizer.source.sop), source.eop.eq(depacketizer.source.eop), source.src_port.eq(depacketizer.source.src_port), source.dst_port.eq(depacketizer.source.dst_port), diff --git a/liteeth/frontend/etherbone.py b/liteeth/frontend/etherbone.py index 2454e08..6e5fd4c 100644 --- a/liteeth/frontend/etherbone.py +++ b/liteeth/frontend/etherbone.py @@ -23,7 +23,6 @@ class LiteEthEtherbonePacketTX(Module): self.submodules.packetizer = packetizer = LiteEthEtherbonePacketPacketizer() self.comb += [ packetizer.sink.stb.eq(sink.stb), - packetizer.sink.sop.eq(sink.sop), packetizer.sink.eop.eq(sink.eop), sink.ack.eq(packetizer.sink.ack), @@ -40,7 +39,7 @@ class LiteEthEtherbonePacketTX(Module): self.submodules.fsm = fsm = FSM(reset_state="IDLE") fsm.act("IDLE", packetizer.source.ack.eq(1), - If(packetizer.source.stb & packetizer.source.sop, + If(packetizer.source.stb, packetizer.source.ack.eq(0), NextState("SEND") ) @@ -78,7 +77,7 @@ class LiteEthEtherbonePacketRX(Module): self.submodules.fsm = fsm = FSM(reset_state="IDLE") fsm.act("IDLE", depacketizer.source.ack.eq(1), - If(depacketizer.source.stb & depacketizer.source.sop, + If(depacketizer.source.stb, depacketizer.source.ack.eq(0), NextState("CHECK") ) @@ -96,7 +95,6 @@ class LiteEthEtherbonePacketRX(Module): ) ) self.comb += [ - source.sop.eq(depacketizer.source.sop), source.eop.eq(depacketizer.source.eop), source.pf.eq(depacketizer.source.pf), @@ -151,7 +149,7 @@ class LiteEthEtherboneProbe(Module): self.submodules.fsm = fsm = FSM(reset_state="IDLE") fsm.act("IDLE", sink.ack.eq(1), - If(sink.stb & sink.sop, + If(sink.stb, sink.ack.eq(0), NextState("PROBE_RESPONSE") ) @@ -214,7 +212,7 @@ class LiteEthEtherboneRecordReceiver(Module): fsm.act("IDLE", fifo.source.ack.eq(1), counter_reset.eq(1), - If(fifo.source.stb & fifo.source.sop, + If(fifo.source.stb, base_addr_update.eq(1), If(fifo.source.wcount, NextState("RECEIVE_WRITES") @@ -225,7 +223,6 @@ class LiteEthEtherboneRecordReceiver(Module): ) fsm.act("RECEIVE_WRITES", source.stb.eq(fifo.source.stb), - source.sop.eq(counter == 0), source.eop.eq(counter == fifo.source.wcount-1), source.count.eq(fifo.source.wcount), source.be.eq(fifo.source.byte_enable), @@ -246,14 +243,13 @@ class LiteEthEtherboneRecordReceiver(Module): ) fsm.act("RECEIVE_BASE_RET_ADDR", counter_reset.eq(1), - If(fifo.source.stb & fifo.source.sop, + If(fifo.source.stb, base_addr_update.eq(1), NextState("RECEIVE_READS") ) ) fsm.act("RECEIVE_READS", source.stb.eq(fifo.source.stb), - source.sop.eq(counter == 0), source.eop.eq(counter == fifo.source.rcount-1), source.count.eq(fifo.source.rcount), source.base_addr.eq(base_addr), @@ -283,7 +279,7 @@ class LiteEthEtherboneRecordSender(Module): self.submodules.fsm = fsm = FSM(reset_state="IDLE") fsm.act("IDLE", pbuffer.source.ack.eq(1), - If(pbuffer.source.stb & pbuffer.source.sop, + If(pbuffer.source.stb, pbuffer.source.ack.eq(0), NextState("SEND_BASE_ADDRESS") ) @@ -299,7 +295,6 @@ class LiteEthEtherboneRecordSender(Module): fsm.act("SEND_BASE_ADDRESS", source.stb.eq(pbuffer.source.stb), - source.sop.eq(1), source.eop.eq(0), source.data.eq(pbuffer.source.base_addr), If(source.ack, @@ -308,7 +303,6 @@ class LiteEthEtherboneRecordSender(Module): ) fsm.act("SEND_DATA", source.stb.eq(pbuffer.source.stb), - source.sop.eq(0), source.eop.eq(pbuffer.source.eop), source.data.eq(pbuffer.source.data), If(source.stb & source.ack, @@ -339,10 +333,14 @@ class LiteEthEtherboneRecord(Module): self.comb += receiver.sink.data.eq(reverse_bytes(depacketizer.source.data)) # save last ip address + first = Signal(reset=1) last_ip_address = Signal(32) self.sync += [ - If(sink.stb & sink.sop & sink.ack, - last_ip_address.eq(sink.ip_address) + If(sink.stb & sink.ack, + If(first, + last_ip_address.eq(sink.ip_address), + ), + first.eq(sink.eop) ) ] @@ -378,7 +376,7 @@ class LiteEthEtherboneWishboneMaster(Module): self.submodules.fsm = fsm = FSM(reset_state="IDLE") fsm.act("IDLE", sink.ack.eq(1), - If(sink.stb & sink.sop, + If(sink.stb, sink.ack.eq(0), If(sink.we, NextState("WRITE_DATA") @@ -413,7 +411,6 @@ class LiteEthEtherboneWishboneMaster(Module): ) fsm.act("SEND_DATA", source.stb.eq(sink.stb), - source.sop.eq(sink.sop), source.eop.eq(sink.eop), source.base_addr.eq(sink.base_addr), source.addr.eq(sink.addr), @@ -450,7 +447,7 @@ class LiteEthEtherbone(Module): arbiter = Arbiter([probe.source, record.source], packet.sink) self.submodules += dispatcher, arbiter - # create mmap ŵishbone master + # create mmap wishbone master self.submodules.master = master = LiteEthEtherboneWishboneMaster() self.comb += [ record.receiver.source.connect(master.sink), diff --git a/liteeth/frontend/tty.py b/liteeth/frontend/tty.py index bdcfeb3..861b213 100644 --- a/liteeth/frontend/tty.py +++ b/liteeth/frontend/tty.py @@ -11,7 +11,6 @@ class LiteEthTTYTX(Module): if fifo_depth is None: self.comb += [ source.stb.eq(sink.stb), - source.sop.eq(1), source.eop.eq(1), source.length.eq(1), source.data.eq(sink.data), @@ -45,7 +44,6 @@ class LiteEthTTYTX(Module): ) fsm.act("SEND", source.stb.eq(fifo.source.stb), - source.sop.eq(counter == 0), If(level == 0, source.eop.eq(1), ).Else( diff --git a/liteeth/phy/gmii.py b/liteeth/phy/gmii.py index 9135547..5bfc088 100644 --- a/liteeth/phy/gmii.py +++ b/liteeth/phy/gmii.py @@ -16,9 +16,9 @@ class LiteEthPHYGMIITX(Module): self.sync += pads.tx_er.eq(0) self.sync += [ pads.tx_en.eq(sink.stb), - pads.tx_data.eq(sink.data) + pads.tx_data.eq(sink.data), + sink.ack.eq(1) ] - self.comb += sink.ack.eq(1) class LiteEthPHYGMIIRX(Module): @@ -28,20 +28,12 @@ class LiteEthPHYGMIIRX(Module): # # # dv_d = Signal() - self.sync += dv_d.eq(pads.dv) - - sop = Signal() - eop = Signal() - self.comb += [ - sop.eq(pads.dv & ~dv_d), - eop.eq(~pads.dv & dv_d) - ] self.sync += [ + dv_d.eq(pads.dv), source.stb.eq(pads.dv), - source.sop.eq(sop), source.data.eq(pads.rx_data) ] - self.comb += source.eop.eq(eop) + self.comb += source.eop.eq(~pads.dv & dv_d) class LiteEthPHYGMIICRG(Module, AutoCSR): diff --git a/liteeth/phy/mii.py b/liteeth/phy/mii.py index 0b10247..d0e2cee 100644 --- a/liteeth/phy/mii.py +++ b/liteeth/phy/mii.py @@ -39,11 +39,6 @@ class LiteEthPHYMIIRX(Module): # # # - sop = Signal(reset=1) - sop_set = Signal() - sop_clr = Signal() - self.sync += If(sop_set, sop.eq(1)).Elif(sop_clr, sop.eq(0)) - converter = stream.Converter(converter_description(4), converter_description(8)) converter = ResetInserter()(converter) @@ -54,15 +49,10 @@ class LiteEthPHYMIIRX(Module): converter.sink.stb.eq(1), converter.sink.data.eq(pads.rx_data) ] - self.sync += [ - sop_set.eq(~pads.dv), - sop_clr.eq(pads.dv) - ] self.comb += [ - converter.sink.sop.eq(sop), - converter.sink.eop.eq(~pads.dv) + converter.sink.eop.eq(~pads.dv), + converter.source.connect(source) ] - self.comb += converter.source.connect(source) class LiteEthPHYMIICRG(Module, AutoCSR): diff --git a/liteeth/phy/model.py b/liteeth/phy/model.py index f09e109..ef1049b 100644 --- a/liteeth/phy/model.py +++ b/liteeth/phy/model.py @@ -40,7 +40,6 @@ class LiteEthPHYModel(Module, AutoCSR): self.sync += [ self.source.stb.eq(pads.sink_stb), - self.source.sop.eq(pads.sink_stb & ~self.source.stb), self.source.data.eq(pads.sink_data), ] self.comb += [ diff --git a/liteeth/phy/rmii.py b/liteeth/phy/rmii.py index 77d6607..4eb5141 100644 --- a/liteeth/phy/rmii.py +++ b/liteeth/phy/rmii.py @@ -40,23 +40,16 @@ class LiteEthPHYRMIIRX(Module): # # # - sop = Signal(reset=1) - sop_set = Signal() - sop_clr = Signal() - self.sync += If(sop_set, sop.eq(1)).Elif(sop_clr, sop.eq(0)) - converter = stream.Converter(converter_description(2), converter_description(8)) converter = ResetInserter()(converter) self.submodules += converter converter_sink_stb = Signal() - converter_sink_sop = Signal() converter_sink_data = Signal(2) self.specials += [ MultiReg(converter_sink_stb, converter.sink.stb, n=2), - MultiReg(converter_sink_sop, converter.sink.sop, n=2), MultiReg(converter_sink_data, converter.sink.data, n=2) ] @@ -73,7 +66,6 @@ class LiteEthPHYRMIIRX(Module): fsm.act("IDLE", If(crs_dv & (rx_data != 0b00), converter_sink_stb.eq(1), - converter_sink_sop.eq(1), converter_sink_data.eq(rx_data), NextState("RECEIVE") ).Else( diff --git a/liteeth/phy/s6rgmii.py b/liteeth/phy/s6rgmii.py index 4f05e21..a17c688 100644 --- a/liteeth/phy/s6rgmii.py +++ b/liteeth/phy/s6rgmii.py @@ -59,15 +59,8 @@ class LiteEthPHYRGMIIRX(Module): rx_ctl_d = Signal() self.sync += rx_ctl_d.eq(rx_ctl) - sop = Signal() - eop = Signal() - self.comb += [ - sop.eq(rx_ctl & ~rx_ctl_d), - eop.eq(~rx_ctl & rx_ctl_d) - ] self.sync += [ source.stb.eq(rx_ctl), - source.sop.eq(sop), source.data.eq(rx_data) ] self.comb += source.eop.eq(eop) diff --git a/liteeth/phy/s7rgmii.py b/liteeth/phy/s7rgmii.py index 9034a4c..21ba53e 100644 --- a/liteeth/phy/s7rgmii.py +++ b/liteeth/phy/s7rgmii.py @@ -83,15 +83,10 @@ class LiteEthPHYRGMIIRX(Module): rx_ctl_d = Signal() self.sync += rx_ctl_d.eq(rx_ctl) - sop = Signal() eop = Signal() - self.comb += [ - sop.eq(rx_ctl & ~rx_ctl_d), - eop.eq(~rx_ctl & rx_ctl_d) - ] + self.comb += eop.eq(~rx_ctl & rx_ctl_d) self.sync += [ source.stb.eq(rx_ctl), - source.sop.eq(sop), source.data.eq(rx_data) ] self.comb += source.eop.eq(eop) diff --git a/test/ip_tb.py b/test/ip_tb.py index 36c31e8..e43adee 100644 --- a/test/ip_tb.py +++ b/test/ip_tb.py @@ -45,13 +45,12 @@ class TB(Module): while True: selfp.ip_port.sink.stb = 1 - selfp.ip_port.sink.sop = 1 selfp.ip_port.sink.eop = 1 selfp.ip_port.sink.ip_address = 0x12345678 selfp.ip_port.sink.protocol = udp_protocol selfp.ip_port.source.ack = 1 - if selfp.ip_port.source.stb == 1 and selfp.ip_port.source.sop == 1: + if selfp.ip_port.source.stb == 1 and selfp.ip_port.source.eop == 1: print("packet from IP 0x{:08x}".format(selfp.ip_port.sink.ip_address)) yield diff --git a/test/model/phy.py b/test/model/phy.py index 9fa709f..613cefc 100644 --- a/test/model/phy.py +++ b/test/model/phy.py @@ -8,7 +8,7 @@ def print_phy(s): # PHY model -class PHYstream.Endpoint(PacketStreamer): +class PHYSource(PacketStreamer): def __init__(self, dw): PacketStreamer.__init__(self, eth_phy_description(dw)) @@ -23,7 +23,7 @@ class PHY(Module): self.dw = dw self.debug = debug - self.submodules.phy_source = PHYstream.Endpoint(dw) + self.submodules.phy_source = PHYSource(dw) self.submodules.phy_sink = PHYSink(dw) self.source = self.phy_source.source