diff --git a/liteeth/gen.py b/liteeth/gen.py
index 11f5a3b..402ffd6 100755
--- a/liteeth/gen.py
+++ b/liteeth/gen.py
@@ -205,7 +205,6 @@ class PHYCore(SoCMini):
         else:
             raise ValueError("Unsupported PHY")
         self.submodules.ethphy = ethphy
-        self.add_csr("ethphy")
 
         # Generate timing constraints to ensure the "keep" attribute is properly set
         # on the various clocks. This also adds the constraints to the generated xdc
@@ -240,7 +239,6 @@ class MACCore(PHYCore):
             full_memory_we = core_config.get("full_memory_we", False))
         self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus)
         self.add_memory_region("ethmac", self.mem_map["ethmac"], mac_memsize, type="io")
-        self.add_csr("ethmac")
 
         # Wishbone Interface -----------------------------------------------------------------------
         wb_bus = wishbone.Interface()