diff --git a/liteeth/frontend/stream.py b/liteeth/frontend/stream.py
index d02990d..21385d1 100644
--- a/liteeth/frontend/stream.py
+++ b/liteeth/frontend/stream.py
@@ -58,7 +58,11 @@ class LiteEthStream2UDPTX(LiteXModule):
                 source.ip_address.eq(ip_address),
                 source.length.eq(level * (data_width//8)),
                 source.data.eq(fifo.source.data),
-                source.last_be.eq({32:0b1000, 8:0b1}[data_width]),
+                source.last_be.eq({
+                    32 : 0b1000,
+                    16 : 0b10,
+                    8  : 0b1}[data_width]
+                ),
                 If(source.ready,
                     fifo.source.ready.eq(1),
                     NextValue(counter, counter + 1),
diff --git a/liteeth/gen.py b/liteeth/gen.py
index f90a416..84668c8 100755
--- a/liteeth/gen.py
+++ b/liteeth/gen.py
@@ -134,11 +134,12 @@ _io = [
 
     # SGMII PHY Pads
     ("sgmii", 0,
-        Subsignal("refclk", Pins(1)),
-        Subsignal("txp",    Pins(1)),
-        Subsignal("txn",    Pins(1)),
-        Subsignal("rxp",    Pins(1)),
-        Subsignal("rxn",    Pins(1))
+        Subsignal("refclk",  Pins(1)),
+        Subsignal("txp",     Pins(1)),
+        Subsignal("txn",     Pins(1)),
+        Subsignal("rxp",     Pins(1)),
+        Subsignal("rxn",     Pins(1)),
+        Subsignal("link_up", Pins(1)),
     ),
 ]
 
@@ -249,6 +250,7 @@ class PHYCore(SoCMini):
                 rx_polarity        = 0, # Add support to liteeth_gen if useful.
                 tx_polarity        = 0, # Add support to liteeth_gen if useful.
             )
+            self.comb += ethphy_pads.link_up.eq(ethphy.link_up)
         else:
             raise ValueError("Unsupported PHY")
         self.submodules.ethphy = ethphy