From 18cd5f234ad4ab15bb7fc6c204bd1e028b31233f Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 28 Jun 2023 11:02:37 +0200 Subject: [PATCH 1/2] frontend/stream: Add 16-bit data-width support. --- liteeth/frontend/stream.py | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/liteeth/frontend/stream.py b/liteeth/frontend/stream.py index d02990d..21385d1 100644 --- a/liteeth/frontend/stream.py +++ b/liteeth/frontend/stream.py @@ -58,7 +58,11 @@ class LiteEthStream2UDPTX(LiteXModule): source.ip_address.eq(ip_address), source.length.eq(level * (data_width//8)), source.data.eq(fifo.source.data), - source.last_be.eq({32:0b1000, 8:0b1}[data_width]), + source.last_be.eq({ + 32 : 0b1000, + 16 : 0b10, + 8 : 0b1}[data_width] + ), If(source.ready, fifo.source.ready.eq(1), NextValue(counter, counter + 1), From 15054f6f8eb71a4ce495a60104124e8b44578615 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 28 Jun 2023 11:09:19 +0200 Subject: [PATCH 2/2] liteeth_gen/sgmii: Expose link_up status. --- liteeth/gen.py | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/liteeth/gen.py b/liteeth/gen.py index f90a416..84668c8 100755 --- a/liteeth/gen.py +++ b/liteeth/gen.py @@ -134,11 +134,12 @@ _io = [ # SGMII PHY Pads ("sgmii", 0, - Subsignal("refclk", Pins(1)), - Subsignal("txp", Pins(1)), - Subsignal("txn", Pins(1)), - Subsignal("rxp", Pins(1)), - Subsignal("rxn", Pins(1)) + Subsignal("refclk", Pins(1)), + Subsignal("txp", Pins(1)), + Subsignal("txn", Pins(1)), + Subsignal("rxp", Pins(1)), + Subsignal("rxn", Pins(1)), + Subsignal("link_up", Pins(1)), ), ] @@ -249,6 +250,7 @@ class PHYCore(SoCMini): rx_polarity = 0, # Add support to liteeth_gen if useful. tx_polarity = 0, # Add support to liteeth_gen if useful. ) + self.comb += ethphy_pads.link_up.eq(ethphy.link_up) else: raise ValueError("Unsupported PHY") self.submodules.ethphy = ethphy