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phy/k7_1000basex: Replace specific TX/RX MMCM with S7MMCM.

This commit is contained in:
Florent Kermarrec 2023-06-13 14:48:55 +02:00
parent 9a67f4ea6b
commit 5400515a1e
1 changed files with 22 additions and 68 deletions
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82
liteeth/phy/k7_1000basex.py
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@ -10,6 +10,8 @@ from migen.genlib.cdc import PulseSynchronizer
from litex.gen import * from litex.gen import *
from litex.soc.cores.clock import S7MMCM
from liteiclink.transceiver.gtx_7series import GTXChannelPLL, GTXTXInit, GTXRXInit from liteiclink.transceiver.gtx_7series import GTXChannelPLL, GTXTXInit, GTXRXInit
from liteeth.common import * from liteeth.common import *
@ -86,11 +88,13 @@ class K7_1000BASEX(LiteXModule):
# GTX transceiver # GTX transceiver
tx_reset = Signal() tx_reset = Signal()
tx_mmcm_locked = Signal() tx_mmcm_locked = Signal()
tx_mmcm_reset = Signal(reset=1)
tx_data = Signal(20) tx_data = Signal(20)
tx_reset_done = Signal() tx_reset_done = Signal()
rx_reset = Signal() rx_reset = Signal()
rx_mmcm_locked = Signal() rx_mmcm_locked = Signal()
rx_mmcm_reset = Signal(reset=1)
rx_data = Signal(20) rx_data = Signal(20)
rx_reset_done = Signal() rx_reset_done = Signal()
@ -744,71 +748,21 @@ class K7_1000BASEX(LiteXModule):
o_O = rxoutclk_rebuffer o_O = rxoutclk_rebuffer
) )
tx_mmcm_fb = Signal() # TX MMCM.
tx_mmcm_reset = Signal(reset=1) self.tx_mmcm = tx_mmcm = S7MMCM()
clk_tx_unbuf = Signal() tx_mmcm.register_clkin(txoutclk_rebuffer, 62.5e6)
clk_tx_half_unbuf = Signal() tx_mmcm.create_clkout(self.cd_eth_tx_half, 62.5e6, buf="bufh", with_reset=False)
self.specials += [ tx_mmcm.create_clkout(self.cd_eth_tx, 125.0e6, buf="bufh", with_reset=True)
Instance("MMCME2_BASE", self.comb += tx_mmcm.reset.eq(tx_mmcm_reset)
p_CLKIN1_PERIOD = 16.0, self.comb += tx_mmcm_locked.eq(tx_mmcm.locked)
i_CLKIN1 = txoutclk_rebuffer,
i_RST = tx_mmcm_reset,
o_CLKFBOUT = tx_mmcm_fb, # RX MMCM.
i_CLKFBIN = tx_mmcm_fb, self.rx_mmcm = rx_mmcm = S7MMCM()
rx_mmcm.register_clkin(rxoutclk_rebuffer, 62.5e6)
p_CLKFBOUT_MULT_F = 16, rx_mmcm.create_clkout(self.cd_eth_rx_half, 62.5e6, buf="bufg", with_reset=False)
o_LOCKED = tx_mmcm_locked, rx_mmcm.create_clkout(self.cd_eth_rx, 125.0e6, buf="bufg", with_reset=True)
p_DIVCLK_DIVIDE = 1, self.comb += rx_mmcm.reset.eq(rx_mmcm_reset)
self.comb += rx_mmcm_locked.eq(rx_mmcm.locked)
p_CLKOUT0_DIVIDE_F = 16,
o_CLKOUT0 = clk_tx_half_unbuf,
p_CLKOUT1_DIVIDE = 8,
o_CLKOUT1 = clk_tx_unbuf,
),
Instance("BUFH",
i_I = clk_tx_half_unbuf,
o_O = self.cd_eth_tx_half.clk,
),
Instance("BUFH",
i_I = clk_tx_unbuf,
o_O = self.cd_eth_tx.clk,
),
AsyncResetSynchronizer(self.cd_eth_tx, ~tx_mmcm_locked)
]
rx_mmcm_fb = Signal()
rx_mmcm_reset = Signal(reset=1)
clk_rx_unbuf = Signal()
clk_rx_half_unbuf = Signal()
self.specials += [
Instance("MMCME2_BASE",
p_CLKIN1_PERIOD = 16.0,
i_CLKIN1 = rxoutclk_rebuffer,
i_RST = rx_mmcm_reset,
o_CLKFBOUT = rx_mmcm_fb,
i_CLKFBIN = rx_mmcm_fb,
p_CLKFBOUT_MULT_F = 16,
o_LOCKED = rx_mmcm_locked,
p_DIVCLK_DIVIDE = 1,
p_CLKOUT0_DIVIDE_F = 16,
o_CLKOUT0 = clk_rx_half_unbuf,
p_CLKOUT1_DIVIDE = 8,
o_CLKOUT1 = clk_rx_unbuf,
),
Instance("BUFG",
i_I = clk_rx_half_unbuf,
o_O = self.cd_eth_rx_half.clk,
),
Instance("BUFG",
i_I = clk_rx_unbuf,
o_O = self.cd_eth_rx.clk,
),
AsyncResetSynchronizer(self.cd_eth_rx, ~rx_mmcm_locked)
]
# Transceiver init # Transceiver init
tx_init = GTXTXInit(sys_clk_freq, buffer_enable=True) tx_init = GTXTXInit(sys_clk_freq, buffer_enable=True)