From 54d7c6620b62551f8ce9317ac1c3934e245f7c41 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 9 Dec 2015 12:33:24 +0100 Subject: [PATCH] phy: add mdio on all phys --- liteeth/phy/common.py | 25 +++++++++++++++++++++++++ liteeth/phy/gmii.py | 5 +++++ liteeth/phy/gmii_mii.py | 5 +++++ liteeth/phy/mii.py | 5 +++++ liteeth/phy/rmii.py | 5 +++++ liteeth/phy/s6rgmii.py | 5 +++++ liteeth/phy/s7rgmii.py | 5 +++++ 7 files changed, 55 insertions(+) create mode 100644 liteeth/phy/common.py diff --git a/liteeth/phy/common.py b/liteeth/phy/common.py new file mode 100644 index 0000000..fbb1d85 --- /dev/null +++ b/liteeth/phy/common.py @@ -0,0 +1,25 @@ +from liteeth.common import * + +from litex.gen.genlib.cdc import MultiReg +from litex.gen.fhdl.specials import Tristate + + +class LiteEthPHYMDIO(Module, AutoCSR): + def __init__(self, pads): + self._w = CSRStorage(3, name="w") + self._r = CSRStatus(1, name="r") + + # # # + + data_w = Signal() + data_oe = Signal() + data_r = Signal() + self.comb +=[ + pads.mdc.eq(self._w.storage[0]), + data_oe.eq(self._w.storage[1]), + data_w.eq(self._w.storage[2]) + ] + self.specials += [ + MultiReg(data_r, self._r.status[0]), + Tristate(pads.mdio, data_w, data_oe, data_r) + ] diff --git a/liteeth/phy/gmii.py b/liteeth/phy/gmii.py index 10c72c0..f5fadf8 100644 --- a/liteeth/phy/gmii.py +++ b/liteeth/phy/gmii.py @@ -3,6 +3,8 @@ from liteeth.common import * from litex.gen.genlib.io import DDROutput from litex.gen.genlib.resetsync import AsyncResetSynchronizer +from liteeth.phy.common import LiteEthPHYMDIO + class LiteEthPHYGMIITX(Module): def __init__(self, pads, pads_register=True): @@ -98,3 +100,6 @@ class LiteEthPHYGMII(Module, AutoCSR): self.submodules.tx = ClockDomainsRenamer("eth_tx")(LiteEthPHYGMIITX(pads)) self.submodules.rx = ClockDomainsRenamer("eth_rx")(LiteEthPHYGMIIRX(pads)) self.sink, self.source = self.tx.sink, self.rx.source + + if hasattr(pads, "mdc"): + self.submodules.mdio = LiteEthPHYMDIO(pads) diff --git a/liteeth/phy/gmii_mii.py b/liteeth/phy/gmii_mii.py index b003966..7df12c8 100644 --- a/liteeth/phy/gmii_mii.py +++ b/liteeth/phy/gmii_mii.py @@ -8,6 +8,8 @@ from litex.gen.genlib.cdc import PulseSynchronizer from litex.soc.interconnect.stream import Multiplexer, Demultiplexer +from liteeth.phy.common import LiteEthPHYMDIO + modes = { "GMII": 0, @@ -168,3 +170,6 @@ class LiteEthPHYGMIIMII(Module, AutoCSR): self.submodules.tx = ClockDomainsRenamer("eth_tx")(LiteEthPHYGMIIMIITX(pads, mode)) self.submodules.rx = ClockDomainsRenamer("eth_rx")(LiteEthPHYGMIIMIIRX(pads, mode)) self.sink, self.source = self.tx.sink, self.rx.source + + if hasattr(pads, "mdc"): + self.submodules.mdio = LiteEthPHYMDIO(pads) \ No newline at end of file diff --git a/liteeth/phy/mii.py b/liteeth/phy/mii.py index b4089bd..3fd2de8 100644 --- a/liteeth/phy/mii.py +++ b/liteeth/phy/mii.py @@ -2,6 +2,8 @@ from liteeth.common import * from litex.gen.genlib.resetsync import AsyncResetSynchronizer +from liteeth.phy.common import LiteEthPHYMDIO + def converter_description(dw): payload_layout = [("data", dw)] @@ -108,3 +110,6 @@ class LiteEthPHYMII(Module, AutoCSR): self.submodules.tx = ClockDomainsRenamer("eth_tx")(LiteEthPHYMIITX(pads)) self.submodules.rx = ClockDomainsRenamer("eth_rx")(LiteEthPHYMIIRX(pads)) self.sink, self.source = self.tx.sink, self.rx.source + + if hasattr(pads, "mdc"): + self.submodules.mdio = LiteEthPHYMDIO(pads) diff --git a/liteeth/phy/rmii.py b/liteeth/phy/rmii.py index 2944d5d..92da7be 100644 --- a/liteeth/phy/rmii.py +++ b/liteeth/phy/rmii.py @@ -5,6 +5,8 @@ from litex.gen.genlib.misc import WaitTimer from litex.gen.genlib.io import DDROutput from litex.gen.genlib.resetsync import AsyncResetSynchronizer +from liteeth.phy.common import LiteEthPHYMDIO + def converter_description(dw): payload_layout = [("data", dw)] @@ -132,3 +134,6 @@ class LiteEthPHYRMII(Module, AutoCSR): self.submodules.tx = ClockDomainsRenamer("eth_tx")(LiteEthPHYRMIITX(pads)) self.submodules.rx = ClockDomainsRenamer("eth_rx")(LiteEthPHYRMIIRX(pads)) self.sink, self.source = self.tx.sink, self.rx.source + + if hasattr(pads, "mdc"): + self.submodules.mdio = LiteEthPHYMDIO(pads) diff --git a/liteeth/phy/s6rgmii.py b/liteeth/phy/s6rgmii.py index 1931760..744369d 100644 --- a/liteeth/phy/s6rgmii.py +++ b/liteeth/phy/s6rgmii.py @@ -7,6 +7,8 @@ from litex.gen.genlib.fsm import FSM, NextState from litex.gen.genlib.resetsync import AsyncResetSynchronizer +from liteeth.phy.common import LiteEthPHYMDIO + class LiteEthPHYRGMIITX(Module): def __init__(self, pads, pads_register=True): @@ -159,3 +161,6 @@ class LiteEthPHYRGMII(Module, AutoCSR): self.submodules.tx = RenameClockDomains(LiteEthPHYRGMIITX(pads), "eth_tx") self.submodules.rx = RenameClockDomains(LiteEthPHYRGMIIRX(pads), "eth_rx") self.sink, self.source = self.tx.sink, self.rx.source + + if hasattr(pads, "mdc"): + self.submodules.mdio = LiteEthPHYMDIO(pads) diff --git a/liteeth/phy/s7rgmii.py b/liteeth/phy/s7rgmii.py index 24aa4a9..9e4446f 100644 --- a/liteeth/phy/s7rgmii.py +++ b/liteeth/phy/s7rgmii.py @@ -7,6 +7,8 @@ from litex.gen.genlib.fsm import FSM, NextState from litex.gen.genlib.resetsync import AsyncResetSynchronizer +from liteeth.phy.common import LiteEthPHYMDIO + class LiteEthPHYRGMIITX(Module): def __init__(self, pads, pads_register=True): @@ -174,3 +176,6 @@ class LiteEthPHYRGMII(Module, AutoCSR): self.submodules.tx = ClockDomainsRenamer("eth_tx")(LiteEthPHYRGMIITX(pads)) self.submodules.rx = ClockDomainsRenamer("eth_rx")(LiteEthPHYRGMIIRX(pads)) self.sink, self.source = self.tx.sink, self.rx.source + + if hasattr(pads, "mdc"): + self.submodules.mdio = LiteEthPHYMDIO(pads)