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liteeth/phy/rmii: Move crs first/last detection outside of FSM.

This commit is contained in:
Florent Kermarrec 2024-09-23 11:30:57 +02:00
parent 1c89387d09
commit 5538c87115
1 changed files with 7 additions and 5 deletions
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12
liteeth/phy/rmii.py
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@ -61,9 +61,12 @@ class LiteEthPHYRMIIRX(LiteXModule):
rx_data.eq(pads.rx_data) rx_data.eq(pads.rx_data)
] ]
crs_first = (crs_dv & (rx_data != 0b00))
crs_last = (~crs_dv & ~crs_dv_d) # End of frame when 2 consecutives 0 on crs_dv.
self.fsm = fsm = FSM(reset_state="IDLE") self.fsm = fsm = FSM(reset_state="IDLE")
fsm.act("IDLE", fsm.act("IDLE",
If(crs_dv & (rx_data != 0b00), If(crs_first,
delay.sink.valid.eq(1), delay.sink.valid.eq(1),
delay.sink.data.eq(rx_data), delay.sink.data.eq(rx_data),
NextState("RECEIVE") NextState("RECEIVE")
@ -74,10 +77,9 @@ class LiteEthPHYRMIIRX(LiteXModule):
fsm.act("RECEIVE", fsm.act("RECEIVE",
delay.sink.valid.eq(1), delay.sink.valid.eq(1),
delay.sink.data.eq(rx_data), delay.sink.data.eq(rx_data),
# End of frame when 2 consecutives 0 on crs_dv. If(crs_last,
If(~(crs_dv | crs_dv_d), converter.sink.last.eq(1),
converter.sink.last.eq(1), NextState("IDLE")
NextState("IDLE")
) )
) )
self.comb += converter.source.connect(source) self.comb += converter.source.connect(source)