From 5583fe5543e552da5338d0089fc6ec909e571e13 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 24 Feb 2016 23:51:31 +0100 Subject: [PATCH] phy/s6rgmii: RenameClockDomains --> ClockDomainsRenamer --- liteeth/phy/s6rgmii.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/liteeth/phy/s6rgmii.py b/liteeth/phy/s6rgmii.py index b2e5206..6e89833 100644 --- a/liteeth/phy/s6rgmii.py +++ b/liteeth/phy/s6rgmii.py @@ -152,8 +152,8 @@ class LiteEthPHYRGMII(Module, AutoCSR): def __init__(self, clock_pads, pads, with_hw_init_reset=True): self.dw = 8 self.submodules.crg = LiteEthPHYRGMIICRG(clock_pads, pads, with_hw_init_reset) - self.submodules.tx = RenameClockDomains(LiteEthPHYRGMIITX(pads), "eth_tx") - self.submodules.rx = RenameClockDomains(LiteEthPHYRGMIIRX(pads), "eth_rx") + self.submodules.tx = ClockDomainsRenamer("eth_tx")(LiteEthPHYRGMIITX(pads)) + self.submodules.rx = ClockDomainsRenamer("eth_rx")(LiteEthPHYRGMIIRX(pads)) self.sink, self.source = self.tx.sink, self.rx.source if hasattr(pads, "mdc"):