diff --git a/liteeth/phy/trionrgmii.py b/liteeth/phy/trionrgmii.py
index d6d2884..edd5e8e 100644
--- a/liteeth/phy/trionrgmii.py
+++ b/liteeth/phy/trionrgmii.py
@@ -36,7 +36,7 @@ class LiteEthPHYRGMIITX(LiteXModule):
                 i1  = tx_data_h[i],
                 i2  = tx_data_l[i],
                 o   = pads.tx_data[i],
-                clk = f"auto_eth{n}_tx_clk", # FIXME: Use Clk Signal.
+                clk = ClockSignal("eth_tx")
             )
 
         # TX Ctl IOs.
@@ -47,7 +47,7 @@ class LiteEthPHYRGMIITX(LiteXModule):
             i1  = tx_ctl_h,
             i2  = tx_ctl_l,
             o   = pads.tx_ctl,
-            clk = f"auto_eth{n}_tx_clk", # FIXME: Use Clk Signal.
+            clk = ClockSignal("eth_tx")
         )
 
         # Logic.
@@ -80,7 +80,7 @@ class LiteEthPHYRGMIIRX(LiteXModule):
                 i   = pads.rx_data[i],
                 o1  = rx_data_h[i],
                 o2  = rx_data_l[i],
-                clk = f"auto_eth{n}_rx_clk", # FIXME: Use Clk Signal.
+                clk = ClockSignal("eth_rx")
             )
 
         # RX Ctl IOs.
@@ -91,7 +91,7 @@ class LiteEthPHYRGMIIRX(LiteXModule):
             i   = pads.rx_ctl,
             o1  = rx_ctl_h,
             o2  = rx_ctl_l,
-            clk = f"auto_eth{n}_rx_clk", # FIXME: Use Clk Signal.
+            clk = ClockSignal("eth_rx")
         )
 
         rx_ctl   = rx_ctl_h