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phy/trionrgmii.py: DDRInput/DDROutput switch clk to a ClockSignal

This commit is contained in:
Gwenhael Goavec-Merou 2024-09-10 08:09:03 +02:00
parent ea07f5c421
commit 577a47222c
1 changed files with 4 additions and 4 deletions
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8
liteeth/phy/trionrgmii.py
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@ -36,7 +36,7 @@ class LiteEthPHYRGMIITX(LiteXModule):
i1 = tx_data_h[i], i1 = tx_data_h[i],
i2 = tx_data_l[i], i2 = tx_data_l[i],
o = pads.tx_data[i], o = pads.tx_data[i],
clk = f"auto_eth{n}_tx_clk", # FIXME: Use Clk Signal. clk = ClockSignal("eth_tx")
) )
# TX Ctl IOs. # TX Ctl IOs.
@ -47,7 +47,7 @@ class LiteEthPHYRGMIITX(LiteXModule):
i1 = tx_ctl_h, i1 = tx_ctl_h,
i2 = tx_ctl_l, i2 = tx_ctl_l,
o = pads.tx_ctl, o = pads.tx_ctl,
clk = f"auto_eth{n}_tx_clk", # FIXME: Use Clk Signal. clk = ClockSignal("eth_tx")
) )
# Logic. # Logic.
@ -80,7 +80,7 @@ class LiteEthPHYRGMIIRX(LiteXModule):
i = pads.rx_data[i], i = pads.rx_data[i],
o1 = rx_data_h[i], o1 = rx_data_h[i],
o2 = rx_data_l[i], o2 = rx_data_l[i],
clk = f"auto_eth{n}_rx_clk", # FIXME: Use Clk Signal. clk = ClockSignal("eth_rx")
) )
# RX Ctl IOs. # RX Ctl IOs.
@ -91,7 +91,7 @@ class LiteEthPHYRGMIIRX(LiteXModule):
i = pads.rx_ctl, i = pads.rx_ctl,
o1 = rx_ctl_h, o1 = rx_ctl_h,
o2 = rx_ctl_l, o2 = rx_ctl_l,
clk = f"auto_eth{n}_rx_clk", # FIXME: Use Clk Signal. clk = ClockSignal("eth_rx")
) )
rx_ctl = rx_ctl_h rx_ctl = rx_ctl_h