Hardware
/
liteeth
mirror of https://github.com/enjoy-digital/liteeth.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

phy/trionrgmii.py: DDRInput/DDROutput switch clk to a ClockSignal

This commit is contained in:
Gwenhael Goavec-Merou 2024-09-10 08:09:03 +02:00
parent ea07f5c421
commit 577a47222c
1 changed files with 4 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
liteeth/phy/trionrgmii.py
View File

@ -36,7 +36,7 @@ class LiteEthPHYRGMIITX(LiteXModule):
i1 = tx_data_h[i],
i2 = tx_data_l[i],
o = pads.tx_data[i],
clk = f"auto_eth{n}_tx_clk", # FIXME: Use Clk Signal.
clk = ClockSignal("eth_tx")
)
# TX Ctl IOs.
@ -47,7 +47,7 @@ class LiteEthPHYRGMIITX(LiteXModule):
i1 = tx_ctl_h,
i2 = tx_ctl_l,
o = pads.tx_ctl,
clk = f"auto_eth{n}_tx_clk", # FIXME: Use Clk Signal.
clk = ClockSignal("eth_tx")
)
# Logic.
@ -80,7 +80,7 @@ class LiteEthPHYRGMIIRX(LiteXModule):
i = pads.rx_data[i],
o1 = rx_data_h[i],
o2 = rx_data_l[i],
clk = f"auto_eth{n}_rx_clk", # FIXME: Use Clk Signal.
clk = ClockSignal("eth_rx")
)
# RX Ctl IOs.
@ -91,7 +91,7 @@ class LiteEthPHYRGMIIRX(LiteXModule):
i = pads.rx_ctl,
o1 = rx_ctl_h,
o2 = rx_ctl_l,
clk = f"auto_eth{n}_rx_clk", # FIXME: Use Clk Signal.
clk = ClockSignal("eth_rx")
)
rx_ctl = rx_ctl_h