From 57b671692dc1d564e0d00f01c7acb911c1458d34 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 21 Oct 2015 23:39:27 +0200 Subject: [PATCH] core/ip: use decorators on LiteEthIPV4Checksum (cleanup) --- liteeth/core/ip.py | 14 ++++---------- 1 file changed, 4 insertions(+), 10 deletions(-) diff --git a/liteeth/core/ip.py b/liteeth/core/ip.py index 314873e..2d4f2ca 100644 --- a/liteeth/core/ip.py +++ b/liteeth/core/ip.py @@ -35,10 +35,10 @@ class LiteEthIPV4Crossbar(LiteEthCrossbar): # ip checksum +@DecorateModule(InsertReset) +@DecorateModule(InsertCE) class LiteEthIPV4Checksum(Module): def __init__(self, words_per_clock_cycle=1, skip_checksum=False): - self.reset = Signal() # XXX FIXME InsertReset generates incorrect verilog - self.ce = Signal() # XXX FIXME InsertCE generates incorrect verilog self.header = Signal(ipv4_header.length*8) self.value = Signal(16) self.done = Signal() @@ -59,12 +59,7 @@ class LiteEthIPV4Checksum(Module): if (i%words_per_clock_cycle) != 0: self.comb += r_next_eq else: - self.sync += \ - If(self.reset, - r_next.eq(0) - ).Elif(self.ce & ~self.done, - r_next_eq - ) + self.sync += If(~self.done, r_next_eq) n_cycles += 1 s, r = s_next, r_next self.comb += self.value.eq(~Cat(r[8:16], r[:8])) @@ -73,8 +68,7 @@ class LiteEthIPV4Checksum(Module): n_cycles += 1 self.submodules.counter = counter = Counter(max=n_cycles+1) self.comb += [ - counter.reset.eq(self.reset), - counter.ce.eq(self.ce & ~self.done), + counter.ce.eq(~self.done), self.done.eq(counter.value == n_cycles) ]