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phy/1000basex: Use pll.config["d"] to compute TX_PROGDIV_CFG/RX_PROGDIV_CFG to fix behavior with 200MHz ref_clk_freq.

This commit is contained in:
Florent Kermarrec 2024-07-10 16:21:11 +02:00
parent e0f053e7a2
commit 583137eaf3
3 changed files with 24 additions and 6 deletions
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10
liteeth/phy/ku_1000basex.py
View File

@ -356,7 +356,10 @@ class KU_1000BASEX(LiteXModule):
p_RX_FABINT_USRCLK_FLOP = 0b0, p_RX_FABINT_USRCLK_FLOP = 0b0,
p_RX_INT_DATAWIDTH = 0, p_RX_INT_DATAWIDTH = 0,
p_RX_PMA_POWER_SAVE = 0b0, p_RX_PMA_POWER_SAVE = 0b0,
p_RX_PROGDIV_CFG = {1.25e9 : 20.0, 3.125e9 : 10.0}[self.linerate], p_RX_PROGDIV_CFG = {
1.25e9 : 20.0*pll.config["d"]/4,
3.125e9 : 10.0*pll.config["d"]/4,
}[self.linerate],
p_RX_SAMPLE_PERIOD = 0b111, p_RX_SAMPLE_PERIOD = 0b111,
p_RX_SIG_VALID_DLY = 11, p_RX_SIG_VALID_DLY = 11,
p_RX_SUM_DFETAPREP_EN = 0b0, p_RX_SUM_DFETAPREP_EN = 0b0,
@ -455,7 +458,10 @@ class KU_1000BASEX(LiteXModule):
p_TX_PMADATA_OPT = 0b0, p_TX_PMADATA_OPT = 0b0,
p_TX_PMA_POWER_SAVE = 0b0, p_TX_PMA_POWER_SAVE = 0b0,
p_TX_PROGCLK_SEL = "CPLL", p_TX_PROGCLK_SEL = "CPLL",
p_TX_PROGDIV_CFG = {1.25e9 : 20.0, 3.125e9 : 10.0}[self.linerate], p_TX_PROGDIV_CFG = {
1.25e9 : 20.0*pll.config["d"]/4,
3.125e9 : 10.0*pll.config["d"]/4,
}[self.linerate],
p_TX_QPI_STATUS_EN = 0b0, p_TX_QPI_STATUS_EN = 0b0,
p_TX_RXDETECT_CFG = 0b00000000110010, p_TX_RXDETECT_CFG = 0b00000000110010,
p_TX_RXDETECT_REF = 0b100, p_TX_RXDETECT_REF = 0b100,

10
liteeth/phy/usp_gth_1000basex.py
View File

@ -400,7 +400,10 @@ class USP_GTH_1000BASEX(LiteXModule):
p_RX_INT_DATAWIDTH = 0, p_RX_INT_DATAWIDTH = 0,
p_RX_PMA_POWER_SAVE = 0b0, p_RX_PMA_POWER_SAVE = 0b0,
p_RX_PMA_RSV0 = 0b0000000000000000, p_RX_PMA_RSV0 = 0b0000000000000000,
p_RX_PROGDIV_CFG = {1.25e9 : 20.0, 3.125e9 : 10.0}[self.linerate], p_RX_PROGDIV_CFG = {
1.25e9 : 20.0*pll.config["d"]/4,
3.125e9 : 10.0*pll.config["d"]/4,
}[self.linerate],
p_RX_PROGDIV_RATE = 0b0000000000000001, p_RX_PROGDIV_RATE = 0b0000000000000001,
p_RX_RESLOAD_CTRL = 0b0000, p_RX_RESLOAD_CTRL = 0b0000,
p_RX_RESLOAD_OVRD = 0b0, p_RX_RESLOAD_OVRD = 0b0,
@ -513,7 +516,10 @@ class USP_GTH_1000BASEX(LiteXModule):
p_TX_PMA_RSV0 = 0b0000000000001000, p_TX_PMA_RSV0 = 0b0000000000001000,
p_TX_PREDRV_CTRL = 2, p_TX_PREDRV_CTRL = 2,
p_TX_PROGCLK_SEL = "PREPI", p_TX_PROGCLK_SEL = "PREPI",
p_TX_PROGDIV_CFG = {1.25e9 : 20.0, 3.125e9 : 10.0}[self.linerate], p_TX_PROGDIV_CFG = {
1.25e9 : 20.0*pll.config["d"]/4,
3.125e9 : 10.0*pll.config["d"]/4,
}[self.linerate],
p_TX_PROGDIV_RATE = 0b0000000000000001, p_TX_PROGDIV_RATE = 0b0000000000000001,
p_TX_QPI_STATUS_EN = 0b0, p_TX_QPI_STATUS_EN = 0b0,
p_TX_RXDETECT_CFG = 0b00000000110010, p_TX_RXDETECT_CFG = 0b00000000110010,

10
liteeth/phy/usp_gty_1000basex.py
View File

@ -418,7 +418,10 @@ class USP_GTY_1000BASEX(LiteXModule):
p_RX_INT_DATAWIDTH = 0, p_RX_INT_DATAWIDTH = 0,
p_RX_PMA_POWER_SAVE = 0b0, p_RX_PMA_POWER_SAVE = 0b0,
p_RX_PMA_RSV0 = 0b0000000000101111, p_RX_PMA_RSV0 = 0b0000000000101111,
p_RX_PROGDIV_CFG = {1.25e9 : 20.0, 3.125e9 : 10.0}[self.linerate], p_RX_PROGDIV_CFG = {
1.25e9 : 20.0*pll.config["d"]/4,
3.125e9 : 10.0*pll.config["d"]/4,
}[self.linerate],
p_RX_PROGDIV_RATE = 0b0000000000000001, p_RX_PROGDIV_RATE = 0b0000000000000001,
p_RX_RESLOAD_CTRL = 0b0000, p_RX_RESLOAD_CTRL = 0b0000,
p_RX_RESLOAD_OVRD = 0b0, p_RX_RESLOAD_OVRD = 0b0,
@ -530,7 +533,10 @@ class USP_GTY_1000BASEX(LiteXModule):
p_TX_PMA_RSV0 = 0b0000000000000000, p_TX_PMA_RSV0 = 0b0000000000000000,
p_TX_PMA_RSV1 = 0b0000000000000000, p_TX_PMA_RSV1 = 0b0000000000000000,
p_TX_PROGCLK_SEL = "CPLL", p_TX_PROGCLK_SEL = "CPLL",
p_TX_PROGDIV_CFG = {1.25e9 : 20.0, 3.125e9 : 10.0}[self.linerate], p_TX_PROGDIV_CFG = {
1.25e9 : 20.0*pll.config["d"]/4,
3.125e9 : 10.0*pll.config["d"]/4,
}[self.linerate],
p_TX_PROGDIV_RATE = 0b0000000000000001, p_TX_PROGDIV_RATE = 0b0000000000000001,
p_TX_RXDETECT_CFG = 0b00000000110010, p_TX_RXDETECT_CFG = 0b00000000110010,
p_TX_RXDETECT_REF = 5, p_TX_RXDETECT_REF = 5,