Hardware
/
liteeth
mirror of https://github.com/enjoy-digital/liteeth.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

mac/wishbone: Switch to LiteXModule.

This commit is contained in:
Florent Kermarrec 2024-06-25 17:57:16 +02:00
parent 20e892c214
commit 591b77e991
1 changed files with 4 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
liteeth/mac/wishbone.py
View File

@ -8,6 +8,8 @@
import math import math
from litex.gen import *
from liteeth.common import * from liteeth.common import *
from liteeth.mac import sram from liteeth.mac import sram
@ -15,7 +17,7 @@ from litex.soc.interconnect import wishbone
# MAC Wishbone Interface --------------------------------------------------------------------------- # MAC Wishbone Interface ---------------------------------------------------------------------------
class LiteEthMACWishboneInterface(Module, AutoCSR): class LiteEthMACWishboneInterface(LiteXModule):
def __init__(self, dw, nrxslots=2, ntxslots=2, endianness="big", timestamp=None, def __init__(self, dw, nrxslots=2, ntxslots=2, endianness="big", timestamp=None,
rxslots_read_only = True, rxslots_read_only = True,
txslots_write_only = False, txslots_write_only = False,
@ -30,7 +32,7 @@ class LiteEthMACWishboneInterface(Module, AutoCSR):
# Storage in SRAM. # Storage in SRAM.
# ---------------- # ----------------
sram_depth = math.ceil(eth_mtu/(dw//8)) sram_depth = math.ceil(eth_mtu/(dw//8))
self.submodules.sram = sram.LiteEthMACSRAM(dw, sram_depth, nrxslots, ntxslots, endianness, timestamp) self.sram = sram.LiteEthMACSRAM(dw, sram_depth, nrxslots, ntxslots, endianness, timestamp)
self.comb += [ self.comb += [
self.sink.connect(self.sram.sink), self.sink.connect(self.sram.sink),
self.sram.source.connect(self.source), self.sram.source.connect(self.source),