liteeth_gen: Add A7_2500BASEX support.
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@ -278,6 +278,7 @@ class PHYCore(SoCMini):
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# SGMII.
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# SGMII.
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elif phy in [
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elif phy in [
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liteeth_phys.A7_1000BASEX,
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liteeth_phys.A7_1000BASEX,
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liteeth_phys.A7_2500BASEX,
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liteeth_phys.K7_1000BASEX,
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liteeth_phys.K7_1000BASEX,
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liteeth_phys.KU_1000BASEX,
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liteeth_phys.KU_1000BASEX,
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liteeth_phys.USP_GTH_1000BASEX,
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liteeth_phys.USP_GTH_1000BASEX,
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@ -285,7 +286,7 @@ class PHYCore(SoCMini):
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]:
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]:
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ethphy_pads = platform.request("sgmii")
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ethphy_pads = platform.request("sgmii")
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# Artix7.
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# Artix7.
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if phy in [liteeth_phys.A7_1000BASEX]:
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if phy in [liteeth_phys.A7_1000BASEX, liteeth_phys.A7_2500BASEX]:
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refclk_freq = core_config.get("refclk_freq", 0)
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refclk_freq = core_config.get("refclk_freq", 0)
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assert refclk_freq in [125e6, 156.25e6]
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assert refclk_freq in [125e6, 156.25e6]
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from liteeth.phy.a7_gtp import QPLLSettings, QPLL
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from liteeth.phy.a7_gtp import QPLLSettings, QPLL
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@ -34,6 +34,7 @@ from liteeth.phy.usrgmii import LiteEthPHYRGMII as LiteEthUSPHYRGMII
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from liteeth.phy.ecp5rgmii import LiteEthPHYRGMII as LiteEthECP5PHYRGMII
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from liteeth.phy.ecp5rgmii import LiteEthPHYRGMII as LiteEthECP5PHYRGMII
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from liteeth.phy.a7_1000basex import A7_1000BASEX
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from liteeth.phy.a7_1000basex import A7_1000BASEX
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from liteeth.phy.a7_2500basex import A7_2500BASEX
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from liteeth.phy.k7_1000basex import K7_1000BASEX
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from liteeth.phy.k7_1000basex import K7_1000BASEX
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from liteeth.phy.ku_1000basex import KU_1000BASEX
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from liteeth.phy.ku_1000basex import KU_1000BASEX
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from liteeth.phy.usp_gth_1000basex import USP_GTH_1000BASEX
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from liteeth.phy.usp_gth_1000basex import USP_GTH_1000BASEX
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