diff --git a/liteeth/mac/wishbone.py b/liteeth/mac/wishbone.py
index 2a49b46..ffc25be 100644
--- a/liteeth/mac/wishbone.py
+++ b/liteeth/mac/wishbone.py
@@ -2,8 +2,6 @@
 # This file is Copyright (c) 2015-2016 Sebastien Bourdeauducq <sb@m-labs.hk>
 # License: BSD
 
-from migen.fhdl.simplify import FullMemoryWE
-
 from liteeth.common import *
 from liteeth.mac import sram
 
@@ -29,8 +27,7 @@ class LiteEthMACWishboneInterface(Module, AutoCSR):
         # Wishbone interface
         wb_rx_sram_ifs = [wishbone.SRAM(self.sram.writer.mems[n], read_only=True)
             for n in range(nrxslots)]
-        # TODO: FullMemoryWE should move to Mibuild
-        wb_tx_sram_ifs = [FullMemoryWE()(wishbone.SRAM(self.sram.reader.mems[n], read_only=False))
+        wb_tx_sram_ifs = [wishbone.SRAM(self.sram.reader.mems[n], read_only=False)
             for n in range(ntxslots)]
         wb_sram_ifs = wb_rx_sram_ifs + wb_tx_sram_ifs