diff --git a/bench/arty.py b/bench/arty.py
index b8e720a..3925c2c 100755
--- a/bench/arty.py
+++ b/bench/arty.py
@@ -42,7 +42,7 @@ class BenchSoC(SoCCore):
             pads       = self.platform.request("eth"),
             with_hw_init_reset = False)
         self.add_csr("ethphy")
-        self.add_etherbone(phy=self.ethphy, buffer_depth=128)
+        self.add_etherbone(phy=self.ethphy, buffer_depth=255)
 
         # SRAM -------------------------------------------------------------------------------------
         self.add_ram("sram", 0x20000000, 0x1000)
diff --git a/bench/colorlight_5a_75b.py b/bench/colorlight_5a_75b.py
index 1a1a3dd..1c3db8d 100755
--- a/bench/colorlight_5a_75b.py
+++ b/bench/colorlight_5a_75b.py
@@ -43,7 +43,7 @@ class BenchSoC(SoCCore):
             tx_delay   = 0e-9,
             with_hw_init_reset = False)
         self.add_csr("ethphy")
-        self.add_etherbone(phy=self.ethphy, buffer_depth=128)
+        self.add_etherbone(phy=self.ethphy, buffer_depth=255)
 
         # SRAM -------------------------------------------------------------------------------------
         self.add_ram("sram", 0x20000000, 0x1000)
diff --git a/bench/genesys2.py b/bench/genesys2.py
index 60cc805..c64d302 100755
--- a/bench/genesys2.py
+++ b/bench/genesys2.py
@@ -42,7 +42,7 @@ class BenchSoC(SoCCore):
             pads       = self.platform.request("eth"),
             with_hw_init_reset = False)
         self.add_csr("ethphy")
-        self.add_etherbone(phy=self.ethphy, buffer_depth=128)
+        self.add_etherbone(phy=self.ethphy, buffer_depth=255)
 
         # SRAM -------------------------------------------------------------------------------------
         self.add_ram("sram", 0x20000000, 0x1000)