diff --git a/bench/arty.py b/bench/arty.py
index 3925c2c..d7f8eb5 100755
--- a/bench/arty.py
+++ b/bench/arty.py
@@ -41,7 +41,6 @@ class BenchSoC(SoCCore):
             clock_pads = self.platform.request("eth_clocks"),
             pads       = self.platform.request("eth"),
             with_hw_init_reset = False)
-        self.add_csr("ethphy")
         self.add_etherbone(phy=self.ethphy, buffer_depth=255)
 
         # SRAM -------------------------------------------------------------------------------------
@@ -52,7 +51,6 @@ class BenchSoC(SoCCore):
         self.submodules.leds = LedChaser(
             pads         = platform.request_all("user_led"),
             sys_clk_freq = sys_clk_freq)
-        self.add_csr("leds")
 
 # Main ---------------------------------------------------------------------------------------------
 
diff --git a/bench/colorlight_5a_75b.py b/bench/colorlight_5a_75b.py
index 1c3db8d..534855a 100755
--- a/bench/colorlight_5a_75b.py
+++ b/bench/colorlight_5a_75b.py
@@ -42,7 +42,6 @@ class BenchSoC(SoCCore):
             pads       = self.platform.request("eth"),
             tx_delay   = 0e-9,
             with_hw_init_reset = False)
-        self.add_csr("ethphy")
         self.add_etherbone(phy=self.ethphy, buffer_depth=255)
 
         # SRAM -------------------------------------------------------------------------------------
@@ -53,7 +52,6 @@ class BenchSoC(SoCCore):
         self.submodules.leds = LedChaser(
             pads         = platform.request_all("user_led_n"),
             sys_clk_freq = sys_clk_freq)
-        self.add_csr("leds")
 
 # Main ---------------------------------------------------------------------------------------------
 
diff --git a/bench/genesys2.py b/bench/genesys2.py
index c64d302..2332f79 100755
--- a/bench/genesys2.py
+++ b/bench/genesys2.py
@@ -41,7 +41,6 @@ class BenchSoC(SoCCore):
             clock_pads = self.platform.request("eth_clocks"),
             pads       = self.platform.request("eth"),
             with_hw_init_reset = False)
-        self.add_csr("ethphy")
         self.add_etherbone(phy=self.ethphy, buffer_depth=255)
 
         # SRAM -------------------------------------------------------------------------------------
@@ -52,7 +51,6 @@ class BenchSoC(SoCCore):
         self.submodules.leds = LedChaser(
             pads         = platform.request_all("user_led"),
             sys_clk_freq = sys_clk_freq)
-        self.add_csr("leds")
 
 # Main ---------------------------------------------------------------------------------------------
 
diff --git a/bench/sim.py b/bench/sim.py
index 53fb793..bedddf1 100755
--- a/bench/sim.py
+++ b/bench/sim.py
@@ -63,7 +63,6 @@ class BenchSoC(SoCCore):
 
         # Etherbone --------------------------------------------------------------------------------
         self.submodules.ethphy = LiteEthPHYModel(self.platform.request("eth"))
-        self.add_csr("ethphy")
         self.add_etherbone(phy=self.ethphy, buffer_depth=255)
 
         # SRAM -------------------------------------------------------------------------------------