From 7e072a997b1e2067bc634002722e9f29b5a41dd0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Fin=20Maa=C3=9F?= Date: Fri, 13 Sep 2024 12:05:38 +0200 Subject: [PATCH] phy: rmii: use ClockSignal(refclk_cd) to drive DDROutput MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit use ClockSignal(refclk_cd) to drive DDROutput. with this the DDROutput can be used on efinix platforms. Signed-off-by: Fin Maaß --- liteeth/phy/rmii.py | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/liteeth/phy/rmii.py b/liteeth/phy/rmii.py index f6de961..457b833 100644 --- a/liteeth/phy/rmii.py +++ b/liteeth/phy/rmii.py @@ -109,14 +109,15 @@ class LiteEthPHYRMIICRG(LiteXModule): # Else use refclk_cd as RMII reference clock (provided by user design). else: - self.comb += self.cd_eth_rx.clk.eq(ClockSignal(refclk_cd)) - self.comb += self.cd_eth_tx.clk.eq(ClockSignal(refclk_cd)) + clk_signal = ClockSignal(refclk_cd) + self.comb += self.cd_eth_rx.clk.eq(clk_signal) + self.comb += self.cd_eth_tx.clk.eq(clk_signal) # Drive clock_pads if provided. if clock_pads is not None: if with_refclk_ddr_output: - self.specials += DDROutput(i1=0, i2=1, o=clock_pads.ref_clk, clk=ClockSignal("eth_tx")) + self.specials += DDROutput(i1=0, i2=1, o=clock_pads.ref_clk, clk=clk_signal) else: - self.comb += clock_pads.ref_clk.eq(~ClockSignal("eth_tx")) # CHEKCME: Keep Invert? + self.comb += clock_pads.ref_clk.eq(~clk_signal) # CHEKCME: Keep Invert? # Reset self.reset = reset = Signal()