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Merge pull request #169 from VOGL-electronic/fix_phy_rmii_efinix 

phy: rmii: use ClockSignal(refclk_cd) to drive DDROutput
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enjoy-digital 2024-09-17 21:20:30 +02:00 committed by GitHub
parent b573e1267c 7e072a997b
commit 5bc0ec00be
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1 changed files with 5 additions and 4 deletions
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liteeth/phy/rmii.py
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@ -109,14 +109,15 @@ class LiteEthPHYRMIICRG(LiteXModule):
# Else use refclk_cd as RMII reference clock (provided by user design). # Else use refclk_cd as RMII reference clock (provided by user design).
else: else:
self.comb += self.cd_eth_rx.clk.eq(ClockSignal(refclk_cd)) clk_signal = ClockSignal(refclk_cd)
self.comb += self.cd_eth_tx.clk.eq(ClockSignal(refclk_cd)) self.comb += self.cd_eth_rx.clk.eq(clk_signal)
self.comb += self.cd_eth_tx.clk.eq(clk_signal)
# Drive clock_pads if provided. # Drive clock_pads if provided.
if clock_pads is not None: if clock_pads is not None:
if with_refclk_ddr_output: if with_refclk_ddr_output:
self.specials += DDROutput(i1=0, i2=1, o=clock_pads.ref_clk, clk=ClockSignal("eth_tx")) self.specials += DDROutput(i1=0, i2=1, o=clock_pads.ref_clk, clk=clk_signal)
else: else:
self.comb += clock_pads.ref_clk.eq(~ClockSignal("eth_tx")) # CHEKCME: Keep Invert? self.comb += clock_pads.ref_clk.eq(~clk_signal) # CHEKCME: Keep Invert?
# Reset # Reset
self.reset = reset = Signal() self.reset = reset = Signal()