liteeth_gen: Allow external QPLL on Artix7 to allow multiple PHYs per Quad.
Requires setting qpll parameter to False in .yml config file.
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0914fb5e51
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@ -145,6 +145,12 @@ _io = [
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),
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),
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# SGMII PHY Pads
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# SGMII PHY Pads
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("sgmii_qpll", 0,
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Subsignal("clk", Pins(1)),
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Subsignal("refclk", Pins(1)),
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Subsignal("reset", Pins(1)),
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Subsignal("lock", Pins(1)),
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),
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("sgmii", 0,
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("sgmii", 0,
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Subsignal("refclk", Pins(1)),
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Subsignal("refclk", Pins(1)),
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Subsignal("rst", Pins(1)),
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Subsignal("rst", Pins(1)),
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@ -293,23 +299,30 @@ class PHYCore(SoCMini):
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if phy in [liteeth_phys.A7_1000BASEX, liteeth_phys.A7_2500BASEX]:
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if phy in [liteeth_phys.A7_1000BASEX, liteeth_phys.A7_2500BASEX]:
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refclk_freq = core_config.get("refclk_freq", 0)
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refclk_freq = core_config.get("refclk_freq", 0)
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assert refclk_freq in [125e6, 156.25e6]
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assert refclk_freq in [125e6, 156.25e6]
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from liteeth.phy.a7_gtp import QPLLSettings, QPLL
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# QPLL.
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qpll_settings = QPLLSettings(
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if core_config.get("qpll", True):
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refclksel = 0b001,
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from liteeth.phy.a7_gtp import QPLLSettings, QPLL
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fbdiv = {
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qpll_settings = QPLLSettings(
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liteeth_phys.A7_1000BASEX : 4,
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refclksel = 0b001,
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liteeth_phys.A7_2500BASEX : 5,
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fbdiv = {
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}[phy],
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liteeth_phys.A7_1000BASEX : 4,
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fbdiv_45 = {
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liteeth_phys.A7_2500BASEX : 5,
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125e6 : 5,
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}[phy],
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156.25e6 : 4,
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fbdiv_45 = {
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}[refclk_freq],
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125e6 : 5,
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refclk_div = 1
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156.25e6 : 4,
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)
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}[refclk_freq],
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qpll = QPLL(ethphy_pads.refclk, qpll_settings)
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refclk_div = 1
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self.submodules += qpll
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)
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qpll = QPLL(ethphy_pads.refclk, qpll_settings)
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self.submodules += qpll
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qpll_channel = qpll.channels[0] # FIXME: Allow 1?
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else:
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qpll_channel = platform.request("sgmii_qpll")
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qpll_channel.index = 0 # FIXME: Allow 1?
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# PHY.
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ethphy = phy(
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ethphy = phy(
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qpll_channel = qpll.channels[0],
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qpll_channel = qpll_channel,
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data_pads = ethphy_pads,
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data_pads = ethphy_pads,
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sys_clk_freq = self.clk_freq,
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sys_clk_freq = self.clk_freq,
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with_csr = False,
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with_csr = False,
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