From 5f14bd4a7f8414b9216c3165d8c6cdb2add916d4 Mon Sep 17 00:00:00 2001 From: Victor Suarez Rovere Date: Mon, 31 Oct 2022 20:43:53 -0300 Subject: [PATCH] add initial support to generate verilog code using wishbone or axi-lite bus standard (depending on the .yml file) --- examples/axi-lite-mii.yml | 19 +++++++++++++++++++ liteeth/gen.py | 25 +++++++++++++++++++------ 2 files changed, 38 insertions(+), 6 deletions(-) create mode 100644 examples/axi-lite-mii.yml diff --git a/examples/axi-lite-mii.yml b/examples/axi-lite-mii.yml new file mode 100644 index 0000000..9f9541d --- /dev/null +++ b/examples/axi-lite-mii.yml @@ -0,0 +1,19 @@ +# +# This file is part of LiteEth. +# +# Copyright (c) 2020 Florent Kermarrec +# Copyright (c) 2022 Victor Suarez Rovere +# SPDX-License-Identifier: BSD-2-Clause + +# PHY ---------------------------------------------------------------------- +phy: LiteEthPHYMII +vendor: xilinx +toolchain: vivado +# Core --------------------------------------------------------------------- +clk_freq: 100e6 +core: axi-lite +endianness: big + +soc: + mem_map: + ethmac: 0x50000000 diff --git a/liteeth/gen.py b/liteeth/gen.py index fa5d283..b797971 100755 --- a/liteeth/gen.py +++ b/liteeth/gen.py @@ -6,6 +6,7 @@ # Copyright (c) 2015-2022 Florent Kermarrec # Copyright (c) 2020 Xiretza # Copyright (c) 2020 Stefan Schrijvers +# Copyright (c) 2022 Victor Suarez Rovere # SPDX-License-Identifier: BSD-2-Clause """ @@ -35,6 +36,7 @@ from litex.build.xilinx.platform import XilinxPlatform from litex.build.lattice.platform import LatticePlatform from litex.soc.interconnect import wishbone +from litex.soc.interconnect import axi from litex.soc.integration.soc_core import * from litex.soc.integration.builder import * from litex.soc.integration.soc import SoCRegion @@ -247,11 +249,22 @@ class MACCore(PHYCore): ntxslots = ntxslots, full_memory_we = core_config.get("full_memory_we", False)) - # Wishbone Interface ----------------------------------------------------------------------- - wb_bus = wishbone.Interface() - platform.add_extension(wb_bus.get_ios("wishbone")) - self.comb += wb_bus.connect_to_pads(self.platform.request("wishbone"), mode="slave") - self.add_wb_master(wb_bus) + eth_bus_standard = core_config["core"] + assert eth_bus_standard in ["wishbone", "axi-lite"] + if eth_bus_standard == "wishbone": + # Wishbone Interface ----------------------------------------------------------------------- + wb_bus = wishbone.Interface() + platform.add_extension(wb_bus.get_ios("wishbone")) + self.comb += wb_bus.connect_to_pads(self.platform.request("wishbone"), mode="slave") + self.add_wb_master(wb_bus) + + if eth_bus_standard == "axi-lite": + # AXI-Lite Interface ----------------------------------------------------------------------- + axil_bus = axi.AXILiteInterface(address_width=32, data_width=32) + platform.add_extension(axil_bus.get_ios("bus")) + self.submodules += axi.Wishbone2AXILite(ethmac.bus, axil_bus) + self.comb += axil_bus.connect_to_pads(self.platform.request("bus"), mode="slave") + self.bus.add_master(master=axil_bus) ethmac_region_size = (nrxslots + ntxslots)*buffer_depth ethmac_region = SoCRegion(origin=self.mem_map.get("ethmac", None), size=ethmac_region_size, cached=False) @@ -388,7 +401,7 @@ def main(): raise ValueError("Unsupported vendor: {}".format(core_config["vendor"])) platform.add_extension(_io) - if core_config["core"] == "wishbone": + if core_config["core"] in ["wishbone", "axi-lite"]: soc = MACCore(platform, core_config) elif core_config["core"] == "udp": soc = UDPCore(platform, core_config)