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Merge pull request #135 from sensille/tx_write_only 

Tx write only
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enjoy-digital 2023-07-03 10:40:39 +02:00 committed by GitHub
parent 15054f6f8e 53799444fd
commit 64627e3707
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GPG Key ID: 4AEE18F83AFDEB23
2 changed files with 4 additions and 2 deletions
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2
liteeth/mac/__init__.py
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@ -18,6 +18,7 @@ class LiteEthMAC(Module, AutoCSR):
with_preamble_crc = True,
nrxslots = 2,
ntxslots = 2,
tx_write_only = False,
hw_mac = None,
timestamp = None,
full_memory_we = False,
@ -55,6 +56,7 @@ class LiteEthMAC(Module, AutoCSR):
ntxslots = ntxslots,
endianness = endianness,
timestamp = timestamp,
tx_write_only = tx_write_only,
)
# On some targets (Intel/Altera), the complex ports aren't inferred
# as block ram, but are created with LUTs. FullMemoryWe splits such

4
liteeth/mac/wishbone.py
View File

@ -16,7 +16,7 @@ from litex.soc.interconnect import wishbone
# MAC Wishbone Interface ---------------------------------------------------------------------------
class LiteEthMACWishboneInterface(Module, AutoCSR):
def __init__(self, dw, nrxslots=2, ntxslots=2, endianness="big", timestamp=None):
def __init__(self, dw, nrxslots=2, ntxslots=2, endianness="big", timestamp=None, tx_write_only=False):
self.sink = stream.Endpoint(eth_phy_description(dw))
self.source = stream.Endpoint(eth_phy_description(dw))
self.bus = wishbone.Interface(data_width=dw)
@ -43,7 +43,7 @@ class LiteEthMACWishboneInterface(Module, AutoCSR):
for n in range(ntxslots):
wb_tx_sram_ifs.append(wishbone.SRAM(
mem_or_size = self.sram.reader.mems[n],
read_only = False,
write_only = tx_write_only,
bus = wishbone.Interface(data_width = dw)
))