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phy/gw5rgmii: fix clks assignment

This commit is contained in:
Gwenhael Goavec-Merou 2024-01-22 06:38:16 +01:00
parent 95081445e7
commit 650433dd4b
1 changed files with 2 additions and 2 deletions
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4
liteeth/phy/gw5rgmii.py
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@ -148,14 +148,14 @@ class LiteEthPHYRGMIICRG(LiteXModule):
# RX Clock # RX Clock
self.cd_eth_rx = ClockDomain() self.cd_eth_rx = ClockDomain()
self.comb += self.cd_eth_rx.clk.eq(clock_pads.rx) self.cd_eth_rx.clk = clock_pads.rx
# TX Clock # TX Clock
self.cd_eth_tx = ClockDomain() self.cd_eth_tx = ClockDomain()
if isinstance(tx_clk, Signal): if isinstance(tx_clk, Signal):
self.comb += self.cd_eth_tx.clk.eq(tx_clk) self.comb += self.cd_eth_tx.clk.eq(tx_clk)
else: else:
self.comb += self.cd_eth_tx.clk.eq(self.cd_eth_rx.clk) self.cd_eth_tx.clk = self.cd_eth_rx.clk
tx_delay_taps = int(tx_delay/12.5e-12) # 12.5ps per tap tx_delay_taps = int(tx_delay/12.5e-12) # 12.5ps per tap
assert tx_delay_taps < 256 assert tx_delay_taps < 256