Hardware
/
liteeth
mirror of https://github.com/enjoy-digital/liteeth.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

liteeth_gen: Add refclk_freq parameter for SGMII/1000BaseX.

This commit is contained in:
Florent Kermarrec 2023-06-23 12:51:15 +02:00
parent eab6b467f7
commit 65ef1930f5
2 changed files with 11 additions and 9 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
examples/udp_usp_gth_sgmii.yml
View File

@ -10,7 +10,8 @@ vendor: xilinx
toolchain : vivado
# Core ---------------------------------------------------------------------
clk_freq: 125e6
refclk_freq : 156.25e6
clk_freq : 25e6
core : udp
data_width : 32

7
liteeth/gen.py
View File

@ -134,7 +134,7 @@ _io = [
# SGMII PHY Pads
("sgmii", 0,
Subsignal("refclk200", Pins(1)),
Subsignal("refclk", Pins(1)),
Subsignal("txp", Pins(1)),
Subsignal("txn", Pins(1)),
Subsignal("rxp", Pins(1)),
@ -241,9 +241,10 @@ class PHYCore(SoCMini):
]:
ethphy_pads = platform.request("sgmii")
ethphy = phy(
refclk_or_clk_pads = ethphy_pads.refclk200,
refclk_or_clk_pads = ethphy_pads.refclk,
data_pads = ethphy_pads,
sys_clk_freq = self.clk_freq,
refclk_freq = core_config.get("refclk_freq", 200e6),
with_csr = False,
rx_polarity = 0, # Add support to liteeth_gen if useful.
tx_polarity = 0, # Add support to liteeth_gen if useful.
@ -438,7 +439,7 @@ def main():
core_config[k] = replaces[r]
if k == "phy":
core_config[k] = getattr(liteeth_phys, core_config[k])
if k in ["clk_freq"]:
if k in ["refclk_freq", "clk_freq"]:
core_config[k] = int(float(core_config[k]))
if k in ["phy_tx_delay", "phy_rx_delay"]:
core_config[k] = float(core_config[k])