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phy/rmii: Also use SDROutput on TX and add comments/simplify.

This commit is contained in:
Florent Kermarrec 2024-09-23 11:53:42 +02:00
parent 3cfbf007ab
commit 66b277a80b
1 changed files with 14 additions and 11 deletions
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25
liteeth/phy/rmii.py
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@ -23,19 +23,22 @@ class LiteEthPHYRMIITX(LiteXModule):
# # # # # #
# Converter: 8-bit to 2-bit.
# --------------------------
self.converter = converter = stream.Converter(8, 2) self.converter = converter = stream.Converter(8, 2)
# Datapath: Sink -> Converter.
# ----------------------------
self.comb += [ self.comb += [
converter.sink.valid.eq(sink.valid), sink.connect(converter.sink, keep={"valid", "ready", "data"}),
converter.sink.data.eq(sink.data),
sink.ready.eq(converter.sink.ready),
converter.source.ready.eq(1), converter.source.ready.eq(1),
] ]
pads.tx_en.reset_less = True
pads.tx_data.reset_less = True # Output (Sync).
self.sync += [ # --------------
pads.tx_en.eq(converter.source.valid), self.specials += SDROutput(i=converter.source.valid, o=pads.tx_en)
pads.tx_data.eq(converter.source.data) for i in range(2):
] self.specials += SDROutput(i=converter.source.data[i], o=pads.tx_data[i])
# LiteEth PHY RMII RX ------------------------------------------------------------------------------ # LiteEth PHY RMII RX ------------------------------------------------------------------------------
@ -45,8 +48,8 @@ class LiteEthPHYRMIIRX(LiteXModule):
# # # # # #
# Input. # Input (Sync).
# ------ # -------------
crs_dv = Signal() crs_dv = Signal()
rx_data = Signal(2) rx_data = Signal(2)
self.specials += SDRInput(i=pads.crs_dv, o=crs_dv) self.specials += SDRInput(i=pads.crs_dv, o=crs_dv)