From 6c3af746e28f55089c9f79966205499af394ae34 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Thu, 11 Mar 2021 11:55:50 +0100 Subject: [PATCH] mac: Use FullMemoryWE on LiteEthMACWishboneInterface to allow correct block ram inteference on Intel/Altera decices. --- liteeth/mac/__init__.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/liteeth/mac/__init__.py b/liteeth/mac/__init__.py index b2bf511..55356c9 100644 --- a/liteeth/mac/__init__.py +++ b/liteeth/mac/__init__.py @@ -37,7 +37,7 @@ class LiteEthMAC(Module, AutoCSR): self.rx_slots = CSRConstant(nrxslots) self.tx_slots = CSRConstant(ntxslots) self.slot_size = CSRConstant(2**bits_for(eth_mtu)) - self.submodules.interface = LiteEthMACWishboneInterface(32, nrxslots, ntxslots, endianness) + self.submodules.interface = FullMemoryWE()(LiteEthMACWishboneInterface(32, nrxslots, ntxslots, endianness)) self.ev, self.bus = self.interface.sram.ev, self.interface.bus self.csrs = self.interface.get_csrs() + self.core.get_csrs() if interface == "hybrid":