From 6d71adae2b3460a9e8d1df0ebc8e7949db55d376 Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Mon, 2 May 2022 13:09:28 +0200
Subject: [PATCH] bench: Use full imports.

---
 bench/arty.py     | 6 +++---
 bench/genesys2.py | 6 +++---
 bench/kcu105.py   | 4 ++--
 bench/xcu1525.py  | 4 ++--
 4 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/bench/arty.py b/bench/arty.py
index 23c9fbe..4bb88fc 100755
--- a/bench/arty.py
+++ b/bench/arty.py
@@ -13,8 +13,8 @@ from migen import *
 from migen.genlib.cdc import MultiReg
 from migen.genlib.misc import WaitTimer
 
-from litex_boards.platforms import arty
-from litex_boards.targets.arty import _CRG
+from litex_boards.platforms import digilent_arty
+from litex_boards.targets.digilent_arty import _CRG
 
 from litex.soc.cores.clock import *
 from litex.soc.interconnect.csr import *
@@ -28,7 +28,7 @@ from liteeth.phy.mii import LiteEthPHYMII
 
 class BenchSoC(SoCCore):
     def __init__(self, sys_clk_freq=int(50e6)):
-        platform = arty.Platform()
+        platform = digilent_arty.Platform()
 
         # SoCMini ----------------------------------------------------------------------------------
         SoCMini.__init__(self, platform, clk_freq=sys_clk_freq,
diff --git a/bench/genesys2.py b/bench/genesys2.py
index 2332f79..3fc6db8 100755
--- a/bench/genesys2.py
+++ b/bench/genesys2.py
@@ -11,8 +11,8 @@ import argparse
 
 from migen import *
 
-from litex_boards.platforms import genesys2
-from litex_boards.targets.genesys2 import _CRG
+from litex_boards.platforms import digilent_genesys2
+from litex_boards.targets.digilent_genesys2 import _CRG
 
 from litex.soc.cores.clock import *
 from litex.soc.interconnect.csr import *
@@ -25,7 +25,7 @@ from liteeth.phy.s7rgmii import LiteEthPHYRGMII
 
 class BenchSoC(SoCCore):
     def __init__(self, sys_clk_freq=int(50e6)):
-        platform = genesys2.Platform()
+        platform = digilent_genesys2.Platform()
 
         # SoCMini ----------------------------------------------------------------------------------
         SoCMini.__init__(self, platform, clk_freq=sys_clk_freq,
diff --git a/bench/kcu105.py b/bench/kcu105.py
index 236d74b..34b676a 100755
--- a/bench/kcu105.py
+++ b/bench/kcu105.py
@@ -12,7 +12,7 @@ import argparse
 from migen import *
 from migen.genlib.resetsync import AsyncResetSynchronizer
 
-from litex_boards.platforms import kcu105
+from litex_boards.platforms import xilinx_kcu105
 
 from litex.soc.cores.clock import *
 from litex.soc.interconnect.csr import *
@@ -41,7 +41,7 @@ class _CRG(Module, AutoCSR):
 
 class BenchSoC(SoCCore):
     def __init__(self, sys_clk_freq=int(125e6)):
-        platform = kcu105.Platform()
+        platform = xilinx_kcu105.Platform()
 
         # SoCMini ----------------------------------------------------------------------------------
         SoCMini.__init__(self, platform, clk_freq=sys_clk_freq,
diff --git a/bench/xcu1525.py b/bench/xcu1525.py
index 763d1dd..a34d696 100755
--- a/bench/xcu1525.py
+++ b/bench/xcu1525.py
@@ -13,7 +13,7 @@ from migen import *
 from migen.genlib.resetsync import AsyncResetSynchronizer
 
 from litex.build.generic_platform import *
-from litex_boards.platforms import xcu1525
+from litex_boards.platforms import sqrl_xcu1525
 
 from litex.soc.cores.clock import *
 from litex.soc.interconnect.csr import *
@@ -54,7 +54,7 @@ class _CRG(Module, AutoCSR):
 
 class BenchSoC(SoCCore):
     def __init__(self, sys_clk_freq=int(125e6)):
-        platform = xcu1525.Platform()
+        platform = sqrl_xcu1525.Platform()
         platform.add_extension(_qsfp_io)
 
         # SoCMini ----------------------------------------------------------------------------------