From 705003e5231436de9a276e8f834564c6fbe90a1e Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Sat, 11 Apr 2020 19:19:03 +0200
Subject: [PATCH] README: switch to markdown.

---
 README => README.md | 48 ++++++++++++++++++++++++++++++---------------
 1 file changed, 32 insertions(+), 16 deletions(-)
 rename README => README.md (71%)

diff --git a/README b/README.md
similarity index 71%
rename from README
rename to README.md
index baf3ae3..804b428 100644
--- a/README
+++ b/README.md
@@ -1,12 +1,17 @@
-                __   _ __      ______  __
-               / /  (_) /____ / __/ /_/ /
-              / /__/ / __/ -_) _// __/ _ \
-             /____/_/\__/\__/___/\__/_//_/
+```
+                                      __   _ __      ______  __
+                                     / /  (_) /____ / __/ /_/ /
+                                    / /__/ / __/ -_) _// __/ _ \
+                                   /____/_/\__/\__/___/\__/_//_/
 
-           Copyright 2012-2018 / EnjoyDigital
+                                 Copyright 2012-2020 / EnjoyDigital
+
+                             A small footprint and configurable Ethernet core
+                                      powered by Migen & LiteX
+```
+
+[![](https://travis-ci.com/enjoy-digital/liteeth.svg?branch=master)](https://travis-ci.com/enjoy-digital/liteeth) ![License](https://img.shields.io/badge/License-BSD%202--Clause-orange.svg)
 
-       A small footprint and configurable Ethernet core
-                powered by Migen & LiteX
 
 [> Intro
 --------
@@ -26,9 +31,11 @@ design flow by generating the verilog rtl that you will use as a standard core.
 PHY:
   - MII, RMII 100Mbps PHYs.
   - GMII / RGMII /1000BaseX 1Gbps PHYs.
+
 Core:
   - Configurable MAC (HW or SW interface)
   - ARP / ICMP / UDP (HW or SW)
+
 Frontend:
   - Etherbone (Wishbone over UDP: Slave or Master support)
 
@@ -52,14 +59,18 @@ enjoy-digital.fr.
 
 [> Getting started
 ------------------
-1. Install Python 3.5, Migen and FPGA vendor's development tools.
-   Get Migen from: https://github.com/m-labs/migen
+1. Install Python 3.6+ and FPGA vendor's development tools.
+2. Install Migen/LiteX and the LiteX's cores:
 
-2. Obtain LiteX and install it:
-  git clone https://github.com/enjoy-digital/litex --recursive
-  cd litex
-  python3 setup.py develop
-  cd ..
+```sh
+$ wget https://raw.githubusercontent.com/enjoy-digital/litex/master/litex_setup.py
+$ chmod +x litex_setup.py
+$ ./litex_setup.py init install --user (--user to install to user directory)
+```
+  Later, if you need to update all repositories:
+```sh
+$ ./litex_setup.py update
+```
 
 3. Check out /examples/versa_ecp5_udp_loopback for a good practical example of how to get
 started with the Liteeth core solo in an FPGA.
@@ -68,9 +79,14 @@ started with the Liteeth core solo in an FPGA.
 --------
 Unit tests are available in ./test/.
 To run all the unit tests:
-  ./setup.py test
+```sh
+$ ./setup.py test
+```
+
 Tests can also be run individually:
-  python3 -m unittest test.test_name
+```sh
+$ python3 -m unittest test.test_name
+```
 
 [> License
 ----------