From 109002985ac58942c77913fb448cc33c9c7a676e Mon Sep 17 00:00:00 2001
From: Leon Schuermann <leon@is.currently.online>
Date: Wed, 1 Sep 2021 19:31:34 +0200
Subject: [PATCH] phy/gmii: add model parameter to skip clock buffers &
 generation

To support a simple GMII simulation, skip clock generation and buffer
logic. This allows to operate a GMII interface over sys_clk. Proper
GMII clocking support can still be added in the simulation, this
should work when setting model = False.

It also sets an attribute "model" such that we can avoid adding
Platform constraints in the rest of the ecosystem (such as
litex/litex/soc/integration/soc.py, add_ethernet and add_etherbone).

Signed-off-by: Leon Schuermann <leon@is.currently.online>
---
 liteeth/phy/gmii.py | 77 ++++++++++++++++++++++++---------------------
 1 file changed, 42 insertions(+), 35 deletions(-)

diff --git a/liteeth/phy/gmii.py b/liteeth/phy/gmii.py
index 51b810c..f6e3697 100644
--- a/liteeth/phy/gmii.py
+++ b/liteeth/phy/gmii.py
@@ -47,7 +47,7 @@ class LiteEthPHYGMIIRX(Module):
 
 
 class LiteEthPHYGMIICRG(Module, AutoCSR):
-    def __init__(self, clock_pads, pads, with_hw_init_reset, mii_mode=0):
+    def __init__(self, clock_pads, pads, with_hw_init_reset, mii_mode=0, model=False):
         self._reset = CSRStorage()
 
         # # #
@@ -55,49 +55,56 @@ class LiteEthPHYGMIICRG(Module, AutoCSR):
         self.clock_domains.cd_eth_rx = ClockDomain()
         self.clock_domains.cd_eth_tx = ClockDomain()
 
-        # RX clock: GMII, MII Use PHY clock_pads.rx as eth_rx_clk.
-        self.specials += Instance("BUFG",
-            i_I = clock_pads.rx,
-            o_O = ClockSignal("eth_rx"),
-        )
-
-        # TX clock: GMII: Drive clock_pads.gtx, clock_pads.tx unused.
-        #           MII : Use PHY clock_pads.tx as eth_tx_clk, do not drive clock_pads.gtx.
-        self.specials += DDROutput(1, mii_mode, clock_pads.gtx, ClockSignal("eth_tx"))
-        eth_tx_clk = Signal()
-        self.comb += [
-            If(mii_mode,
-               eth_tx_clk.eq(clock_pads.tx)
-            ).Else(
-               eth_tx_clk.eq(clock_pads.rx)
+        if not model:
+            # RX clock: GMII, MII Use PHY clock_pads.rx as eth_rx_clk.
+            self.specials += Instance("BUFG",
+                i_I = clock_pads.rx,
+                o_O = ClockSignal("eth_rx"),
             )
-        ]
-        self.specials += Instance("BUFG",
-            i_I = eth_tx_clk,
-            o_O = ClockSignal("eth_tx"),
-        )
 
-        # Reset
-        self.reset = reset = Signal()
-        if with_hw_init_reset:
-            self.submodules.hw_reset = LiteEthPHYHWReset()
-            self.comb += reset.eq(self._reset.storage | self.hw_reset.reset)
+            # TX clock: GMII: Drive clock_pads.gtx, clock_pads.tx unused.
+            #           MII : Use PHY clock_pads.tx as eth_tx_clk, do not drive clock_pads.gtx.
+            self.specials += DDROutput(1, mii_mode, clock_pads.gtx, ClockSignal("eth_tx"))
+            eth_tx_clk = Signal()
+            self.comb += [
+                If(mii_mode,
+                   eth_tx_clk.eq(clock_pads.tx)
+                ).Else(
+                   eth_tx_clk.eq(clock_pads.rx)
+                )
+            ]
+            self.specials += Instance("BUFG",
+                i_I = eth_tx_clk,
+                o_O = ClockSignal("eth_tx"),
+            )
+
+            # Reset
+            self.reset = reset = Signal()
+            if with_hw_init_reset:
+                self.submodules.hw_reset = LiteEthPHYHWReset()
+                self.comb += reset.eq(self._reset.storage | self.hw_reset.reset)
+            else:
+                self.comb += reset.eq(self._reset.storage)
+            if hasattr(pads, "rst_n"):
+                self.comb += pads.rst_n.eq(~reset)
+            self.specials += [
+                AsyncResetSynchronizer(self.cd_eth_tx, reset),
+                AsyncResetSynchronizer(self.cd_eth_rx, reset),
+            ]
         else:
-            self.comb += reset.eq(self._reset.storage)
-        if hasattr(pads, "rst_n"):
-            self.comb += pads.rst_n.eq(~reset)
-        self.specials += [
-            AsyncResetSynchronizer(self.cd_eth_tx, reset),
-            AsyncResetSynchronizer(self.cd_eth_rx, reset),
-        ]
+            self.comb += [
+                self.cd_eth_rx.clk.eq(ClockSignal()),
+                self.cd_eth_tx.clk.eq(ClockSignal()),
+            ]
 
 
 class LiteEthPHYGMII(Module, AutoCSR):
     dw          = 8
     tx_clk_freq = 125e6
     rx_clk_freq = 125e6
-    def __init__(self, clock_pads, pads, with_hw_init_reset=True):
-        self.submodules.crg = LiteEthPHYGMIICRG(clock_pads, pads, with_hw_init_reset)
+    def __init__(self, clock_pads, pads, with_hw_init_reset=True, model=False):
+        self.model = model
+        self.submodules.crg = LiteEthPHYGMIICRG(clock_pads, pads, with_hw_init_reset, model=model)
         self.submodules.tx = ClockDomainsRenamer("eth_tx")(LiteEthPHYGMIITX(pads))
         self.submodules.rx = ClockDomainsRenamer("eth_rx")(LiteEthPHYGMIIRX(pads))
         self.sink, self.source = self.tx.sink, self.rx.source