From 577a47222cf66fcd4ff0f801f61bc182f903e39a Mon Sep 17 00:00:00 2001 From: Gwenhael Goavec-Merou Date: Tue, 10 Sep 2024 08:09:03 +0200 Subject: [PATCH 1/3] phy/trionrgmii.py: DDRInput/DDROutput switch clk to a ClockSignal --- liteeth/phy/trionrgmii.py | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/liteeth/phy/trionrgmii.py b/liteeth/phy/trionrgmii.py index d6d2884..edd5e8e 100644 --- a/liteeth/phy/trionrgmii.py +++ b/liteeth/phy/trionrgmii.py @@ -36,7 +36,7 @@ class LiteEthPHYRGMIITX(LiteXModule): i1 = tx_data_h[i], i2 = tx_data_l[i], o = pads.tx_data[i], - clk = f"auto_eth{n}_tx_clk", # FIXME: Use Clk Signal. + clk = ClockSignal("eth_tx") ) # TX Ctl IOs. @@ -47,7 +47,7 @@ class LiteEthPHYRGMIITX(LiteXModule): i1 = tx_ctl_h, i2 = tx_ctl_l, o = pads.tx_ctl, - clk = f"auto_eth{n}_tx_clk", # FIXME: Use Clk Signal. + clk = ClockSignal("eth_tx") ) # Logic. @@ -80,7 +80,7 @@ class LiteEthPHYRGMIIRX(LiteXModule): i = pads.rx_data[i], o1 = rx_data_h[i], o2 = rx_data_l[i], - clk = f"auto_eth{n}_rx_clk", # FIXME: Use Clk Signal. + clk = ClockSignal("eth_rx") ) # RX Ctl IOs. @@ -91,7 +91,7 @@ class LiteEthPHYRGMIIRX(LiteXModule): i = pads.rx_ctl, o1 = rx_ctl_h, o2 = rx_ctl_l, - clk = f"auto_eth{n}_rx_clk", # FIXME: Use Clk Signal. + clk = ClockSignal("eth_rx") ) rx_ctl = rx_ctl_h From 88387cbd112a1b6b09d1e61e4e66f7b181ad218c Mon Sep 17 00:00:00 2001 From: Gwenhael Goavec-Merou Date: Tue, 10 Sep 2024 11:27:47 +0200 Subject: [PATCH 2/3] phy/trionrgmii.py: use ClockSignal for ClkOutput 'o', remove name parameter when a cd is used --- liteeth/phy/trionrgmii.py | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/liteeth/phy/trionrgmii.py b/liteeth/phy/trionrgmii.py index edd5e8e..3ccc7c5 100644 --- a/liteeth/phy/trionrgmii.py +++ b/liteeth/phy/trionrgmii.py @@ -123,8 +123,9 @@ class LiteEthPHYRGMIICRG(LiteXModule): # Clk Domains. # ------------ - self.cd_eth_rx = ClockDomain() - self.cd_eth_tx = ClockDomain() + self.cd_eth_rx = ClockDomain() + self.cd_eth_tx = ClockDomain() + self.cd_eth_tx_delayed = ClockDomain(reset_less=True) # RX Clk. # ------- @@ -136,17 +137,17 @@ class LiteEthPHYRGMIICRG(LiteXModule): # TX Clk. # ------- self.specials += ClkOutput( - i = f"auto_eth{n}_tx_clk_delayed", # FIXME: Use Clk Signal. + i = ClockSignal("eth_tx_delayed"), o = clock_pads.tx ) # TX PLL. # ------- self.pll = pll = TRIONPLL(platform) - pll.register_clkin(None, freq=125e6, name=f"auto_eth{n}_rx_clk_in0") # FIXME: 0 is to match ClkInput - pll.create_clkout(self.cd_eth_rx, freq=125e6, phase=0, name=f"auto_eth{n}_rx_clk", with_reset=False, is_feedback=True) - pll.create_clkout(self.cd_eth_tx, freq=125e6, phase=0, name=f"auto_eth{n}_tx_clk", with_reset=False) - pll.create_clkout(None, freq=125e6, phase=45, name=f"auto_eth{n}_tx_clk_delayed") + pll.register_clkin(None, freq=125e6, name=f"auto_eth{n}_rx_clk_in0") # FIXME: 0 is to match ClkInput + pll.create_clkout(self.cd_eth_rx, freq=125e6, phase=0, with_reset=False, is_feedback=True) + pll.create_clkout(self.cd_eth_tx, freq=125e6, phase=0, with_reset=False) + pll.create_clkout(self.cd_eth_tx_delayed, freq=125e6, phase=45) # Reset. # ------ From 9496fd229f122f6595ec072c1acfd4acee9e506d Mon Sep 17 00:00:00 2001 From: Gwenhael Goavec-Merou Date: Tue, 10 Sep 2024 11:52:48 +0200 Subject: [PATCH 3/3] phy/titaniumrgmii.py: uses ClockSignal for DDRInput/DDROutput/ClkOutput, added cd for eth_tx_delayed, removed name=xxx for clkout with a cd --- liteeth/phy/titaniumrgmii.py | 23 ++++++++++++----------- 1 file changed, 12 insertions(+), 11 deletions(-) diff --git a/liteeth/phy/titaniumrgmii.py b/liteeth/phy/titaniumrgmii.py index 85a2d76..ed87648 100644 --- a/liteeth/phy/titaniumrgmii.py +++ b/liteeth/phy/titaniumrgmii.py @@ -36,7 +36,7 @@ class LiteEthPHYRGMIITX(LiteXModule): i1 = tx_data_h[i], i2 = tx_data_l[i], o = pads.tx_data[i], - clk = f"auto_eth{n}_tx_clk", # FIXME: Use Clk Signal. + clk = ClockSignal("eth_tx"), ) # TX Ctl IOs. @@ -47,7 +47,7 @@ class LiteEthPHYRGMIITX(LiteXModule): i1 = tx_ctl_h, i2 = tx_ctl_l, o = pads.tx_ctl, - clk = f"auto_eth{n}_tx_clk", # FIXME: Use Clk Signal. + clk = ClockSignal("eth_tx"), ) # Logic. @@ -80,7 +80,7 @@ class LiteEthPHYRGMIIRX(LiteXModule): i = pads.rx_data[i], o1 = rx_data_h[i], o2 = rx_data_l[i], - clk = f"auto_eth{n}_rx_clk", # FIXME: Use Clk Signal. + clk = ClockSignal("eth_rx"), ) # RX Ctl IOs. @@ -91,7 +91,7 @@ class LiteEthPHYRGMIIRX(LiteXModule): i = pads.rx_ctl, o1 = rx_ctl_h, o2 = rx_ctl_l, - clk = f"auto_eth{n}_rx_clk", # FIXME: Use Clk Signal. + clk = ClockSignal("eth_rx"), ) rx_ctl = rx_ctl_h @@ -123,8 +123,9 @@ class LiteEthPHYRGMIICRG(LiteXModule): # Clk Domains. # ------------ - self.cd_eth_rx = ClockDomain() - self.cd_eth_tx = ClockDomain() + self.cd_eth_rx = ClockDomain() + self.cd_eth_tx = ClockDomain() + self.cd_eth_tx_delayed = ClockDomain(reset_less=True) # RX Clk. # ------- @@ -136,17 +137,17 @@ class LiteEthPHYRGMIICRG(LiteXModule): # TX Clk. # ------- self.specials += ClkOutput( - i = f"auto_eth{n}_tx_clk_delayed", # FIXME: Use Clk Signal. + i = ClockSignal("eth_tx_delayed"), o = clock_pads.tx ) # TX PLL. # ------- self.pll = pll = TITANIUMPLL(platform) - pll.register_clkin(None, freq=125e6, name=f"auto_eth{n}_rx_clk_in0") # FIXME: 0 is to match ClkInput - pll.create_clkout(self.cd_eth_rx, freq=125e6, phase=0, name=f"auto_eth{n}_rx_clk", with_reset=False) - pll.create_clkout(self.cd_eth_tx, freq=125e6, phase=0, name=f"auto_eth{n}_tx_clk", with_reset=False) - pll.create_clkout(None, freq=125e6, phase=90, name=f"auto_eth{n}_tx_clk_delayed") + pll.register_clkin(None, freq=125e6, name=f"auto_eth{n}_rx_clk_in0") # FIXME: 0 is to match ClkInput + pll.create_clkout(self.cd_eth_rx, freq=125e6, phase=0, with_reset=False) + pll.create_clkout(self.cd_eth_tx, freq=125e6, phase=0, with_reset=False) + pll.create_clkout(self.cd_eth_tx_delayed, freq=125e6, phase=90) # Reset. # ------