From 7537dcb0fcdbdb325ceaad6e64fa36c194edba3c Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 10 Jul 2023 12:58:44 +0200 Subject: [PATCH] phy/100basex: Rename crg_reset to reset. --- liteeth/phy/a7_1000basex.py | 10 +++++----- liteeth/phy/k7_1000basex.py | 10 +++++----- liteeth/phy/ku_1000basex.py | 10 +++++----- liteeth/phy/usp_gth_1000basex.py | 10 +++++----- liteeth/phy/usp_gty_1000basex.py | 10 +++++----- 5 files changed, 25 insertions(+), 25 deletions(-) diff --git a/liteeth/phy/a7_1000basex.py b/liteeth/phy/a7_1000basex.py index 24efc59..0b619e0 100644 --- a/liteeth/phy/a7_1000basex.py +++ b/liteeth/phy/a7_1000basex.py @@ -40,7 +40,7 @@ class A7_1000BASEX(LiteXModule): self.txoutclk = Signal() self.rxoutclk = Signal() - self.crg_reset = Signal() + self.reset = Signal() if with_csr: self.add_csr() @@ -720,7 +720,7 @@ class A7_1000BASEX(LiteXModule): self.comb += [ qpll_channel.reset.eq(tx_init.qpll_reset), tx_init.qpll_lock.eq(qpll_channel.lock), - tx_reset.eq(tx_init.tx_reset | self.crg_reset) + tx_reset.eq(tx_init.tx_reset | self.reset) ] self.sync += tx_mmcm_reset.eq(~qpll_channel.lock) tx_mmcm_reset.attr.add("no_retiming") @@ -729,7 +729,7 @@ class A7_1000BASEX(LiteXModule): self.submodules += rx_init self.comb += [ rx_init.enable.eq(tx_init.done), - rx_reset.eq(rx_init.rx_reset | self.crg_reset), + rx_reset.eq(rx_init.rx_reset | self.reset), rx_init.rx_pma_reset_done.eq(rx_pma_reset_done), drpaddr.eq(rx_init.drpaddr), @@ -774,5 +774,5 @@ class A7_1000BASEX(LiteXModule): ] def add_csr(self): - self._crg_reset = CSRStorage() - self.comb += self.crg_reset.eq(self._crg_reset.storage) + self._reset = CSRStorage() + self.comb += self.reset.eq(self._reset.storage) diff --git a/liteeth/phy/k7_1000basex.py b/liteeth/phy/k7_1000basex.py index cd1d9b3..1f48a62 100644 --- a/liteeth/phy/k7_1000basex.py +++ b/liteeth/phy/k7_1000basex.py @@ -41,7 +41,7 @@ class K7_1000BASEX(LiteXModule): self.txoutclk = Signal() self.rxoutclk = Signal() - self.crg_reset = Signal() + self.reset = Signal() if with_csr: self.add_csr() @@ -741,7 +741,7 @@ class K7_1000BASEX(LiteXModule): tx_init = ResetInserter()(GTXTXInit(sys_clk_freq, buffer_enable=True)) self.submodules += tx_init self.comb += [ - tx_init.reset.eq(self.crg_reset), + tx_init.reset.eq(self.reset), pll.reset.eq(tx_init.pllreset), tx_init.plllock.eq(pll.lock), tx_reset.eq(tx_init.gtXxreset), @@ -754,7 +754,7 @@ class K7_1000BASEX(LiteXModule): rx_init = ResetInserter()(GTXRXInit(sys_clk_freq, buffer_enable=True)) self.submodules += rx_init self.comb += [ - rx_init.reset.eq(~tx_init.done | self.crg_reset), + rx_init.reset.eq(~tx_init.done | self.reset), rx_init.plllock.eq(pll.lock), rx_reset.eq(rx_init.gtXxreset), rx_init.Xxresetdone.eq(rx_reset_done), @@ -794,5 +794,5 @@ class K7_1000BASEX(LiteXModule): ] def add_csr(self): - self._crg_reset = CSRStorage() - self.comb += self.crg_reset.eq(self._crg_reset.storage) + self._reset = CSRStorage() + self.comb += self.reset.eq(self._reset.storage) diff --git a/liteeth/phy/ku_1000basex.py b/liteeth/phy/ku_1000basex.py index 4153d92..9c7fc42 100644 --- a/liteeth/phy/ku_1000basex.py +++ b/liteeth/phy/ku_1000basex.py @@ -38,7 +38,7 @@ class KU_1000BASEX(LiteXModule): self.txoutclk = Signal() self.rxoutclk = Signal() - self.crg_reset = Signal() + self.reset = Signal() if with_csr: self.add_csr() @@ -837,8 +837,8 @@ class KU_1000BASEX(LiteXModule): ) ] self.comb += [ - tx_reset.eq(pll_reset | ~pll_locked | self.crg_reset), - rx_reset.eq(pll_reset | ~pll_locked | pcs.restart | self.crg_reset) + tx_reset.eq(pll_reset | ~pll_locked | self.reset), + rx_reset.eq(pll_reset | ~pll_locked | pcs.restart | self.reset) ] # Gearbox and PCS connection @@ -852,5 +852,5 @@ class KU_1000BASEX(LiteXModule): ] def add_csr(self): - self._crg_reset = CSRStorage() - self.comb += self.crg_reset.eq(self._crg_reset.storage) + self._reset = CSRStorage() + self.comb += self.reset.eq(self._reset.storage) diff --git a/liteeth/phy/usp_gth_1000basex.py b/liteeth/phy/usp_gth_1000basex.py index 6aef57a..00a2600 100644 --- a/liteeth/phy/usp_gth_1000basex.py +++ b/liteeth/phy/usp_gth_1000basex.py @@ -39,7 +39,7 @@ class USP_GTH_1000BASEX(LiteXModule): self.txoutclk = Signal() self.rxoutclk = Signal() - self.crg_reset = Signal() + self.reset = Signal() if with_csr: self.add_csr() @@ -901,8 +901,8 @@ class USP_GTH_1000BASEX(LiteXModule): ) ] self.comb += [ - tx_reset.eq(pll_reset | ~pll_locked | self.crg_reset), - rx_reset.eq(pll_reset | ~pll_locked | pcs.restart | self.crg_reset) + tx_reset.eq(pll_reset | ~pll_locked | self.reset), + rx_reset.eq(pll_reset | ~pll_locked | pcs.restart | self.reset) ] # Gearbox and PCS connection @@ -917,5 +917,5 @@ class USP_GTH_1000BASEX(LiteXModule): def add_csr(self): - self._crg_reset = CSRStorage() - self.comb += self.crg_reset.eq(self._crg_reset.storage) + self._reset = CSRStorage() + self.comb += self.reset.eq(self._reset.storage) diff --git a/liteeth/phy/usp_gty_1000basex.py b/liteeth/phy/usp_gty_1000basex.py index 9c76091..cf5030e 100644 --- a/liteeth/phy/usp_gty_1000basex.py +++ b/liteeth/phy/usp_gty_1000basex.py @@ -39,7 +39,7 @@ class USP_GTY_1000BASEX(LiteXModule): self.txoutclk = Signal() self.rxoutclk = Signal() - self.crg_reset = Signal() + self.reset = Signal() if with_csr: self.add_csr() @@ -946,8 +946,8 @@ class USP_GTY_1000BASEX(LiteXModule): ) ] self.comb += [ - tx_reset.eq(pll_reset | ~pll_locked | self.crg_reset), - rx_reset.eq(pll_reset | ~pll_locked | pcs.restart | self.crg_reset) + tx_reset.eq(pll_reset | ~pll_locked | self.reset), + rx_reset.eq(pll_reset | ~pll_locked | pcs.restart | self.reset) ] # Gearbox and PCS connection @@ -961,5 +961,5 @@ class USP_GTY_1000BASEX(LiteXModule): ] def add_csr(self): - self._crg_reset = CSRStorage() - self.comb += self.crg_reset.eq(self._crg_reset.storage) + self._reset = CSRStorage() + self.comb += self.reset.eq(self._reset.storage)