replace litex.gen imports with migen imports

example_designs/make.py

@@ -7,8 +7,8 @@ import subprocess
 import struct
 import importlib
 
-from litex.gen.fhdl import verilog
-from litex.gen.fhdl.structure import _Fragment
+from migen.fhdl import verilog
+from migen.fhdl.structure import _Fragment
 
 from litex.build.tools import write_to_file
 from litex.build.xilinx.common import *

example_designs/targets/base.py

@@ -1,4 +1,4 @@
-from litex.gen.genlib.io import CRG
+from migen.genlib.io import CRG
 
 from litex.build.xilinx.vivado import XilinxVivadoToolchain
 from litex.soc.interconnect import wishbone

example_designs/targets/core.py

@@ -2,7 +2,7 @@
 
 import argparse
 
-from litex.gen import *
+from migen import *
 
 from litex.build.generic_platform import *
 from litex.build.xilinx.platform import XilinxPlatform

liteeth/common.py

@@ -1,6 +1,6 @@
 from math import ceil
 
-from litex.gen import *
+from migen import *
 
 from litex.soc.interconnect import stream
 from litex.soc.interconnect.stream import EndpointDescription

liteeth/core/arp.py

@@ -1,6 +1,7 @@
 from liteeth.common import *
 
-from litex.gen.genlib.misc import WaitTimer
+from migen.genlib.misc import WaitTimer
+
 from litex.soc.interconnect.stream_packet import Depacketizer, Packetizer
 
 

liteeth/core/mac/core.py

@@ -1,7 +1,8 @@
 from liteeth.common import *
 from liteeth.core.mac import gap, preamble, crc, padding, last_be
 from liteeth.phy.model import LiteEthPHYModel
-from litex.gen.genlib.cdc import PulseSynchronizer
+
+from migen.genlib.cdc import PulseSynchronizer
 
 
 class LiteEthMACCore(Module, AutoCSR):

liteeth/core/mac/crc.py

@@ -4,7 +4,7 @@ from collections import OrderedDict
 
 from liteeth.common import *
 
-from litex.gen.genlib.misc import chooser, WaitTimer
+from migen.genlib.misc import chooser, WaitTimer
 
 
 class LiteEthMACCRCEngine(Module):

liteeth/core/mac/preamble.py

@@ -1,6 +1,6 @@
 from liteeth.common import *
 
-from litex.gen.genlib.misc import chooser
+from migen.genlib.misc import chooser
 
 
 class LiteEthMACPreambleInserter(Module):

liteeth/core/mac/wishbone.py

@@ -1,8 +1,9 @@
+from migen.fhdl.simplify import FullMemoryWE
+
 from liteeth.common import *
 from liteeth.core.mac import sram
 
 from litex.soc.interconnect import wishbone
-from litex.gen.fhdl.simplify import FullMemoryWE
 
 
 class LiteEthMACWishboneInterface(Module, AutoCSR):

liteeth/phy/common.py

@@ -1,7 +1,7 @@
 from liteeth.common import *
 
-from litex.gen.genlib.cdc import MultiReg
-from litex.gen.fhdl.specials import Tristate
+from migen.genlib.cdc import MultiReg
+from migen.fhdl.specials import Tristate
 
 class LiteEthPHYHWReset(Module):
     def __init__(self):

liteeth/phy/gmii.py

@@ -1,7 +1,7 @@
 from liteeth.common import *
 
-from litex.gen.genlib.io import DDROutput
-from litex.gen.genlib.resetsync import AsyncResetSynchronizer
+from migen.genlib.io import DDROutput
+from migen.genlib.resetsync import AsyncResetSynchronizer
 
 from liteeth.phy.common import *
 

liteeth/phy/gmii_mii.py

@@ -3,8 +3,8 @@ from liteeth.phy.gmii import LiteEthPHYGMIICRG
 from liteeth.phy.mii import LiteEthPHYMIITX, LiteEthPHYMIIRX
 from liteeth.phy.gmii import LiteEthPHYGMIITX, LiteEthPHYGMIIRX
 
-from litex.gen.genlib.io import DDROutput
-from litex.gen.genlib.cdc import PulseSynchronizer
+from migen.genlib.io import DDROutput
+from migen.genlib.cdc import PulseSynchronizer
 
 from litex.soc.interconnect.stream import Multiplexer, Demultiplexer
 

liteeth/phy/mii.py

@@ -1,6 +1,6 @@
 from liteeth.common import *
 
-from litex.gen.genlib.resetsync import AsyncResetSynchronizer
+from migen.genlib.resetsync import AsyncResetSynchronizer
 
 from liteeth.phy.common import *
 

liteeth/phy/rmii.py

@@ -1,9 +1,9 @@
 from liteeth.common import *
 
-from litex.gen.genlib.cdc import MultiReg
-from litex.gen.genlib.misc import WaitTimer
-from litex.gen.genlib.io import DDROutput
-from litex.gen.genlib.resetsync import AsyncResetSynchronizer
+from migen.genlib.cdc import MultiReg
+from migen.genlib.misc import WaitTimer
+from migen.genlib.io import DDROutput
+from migen.genlib.resetsync import AsyncResetSynchronizer
 
 from liteeth.phy.common import *
 

liteeth/phy/s6rgmii.py

@@ -1,11 +1,11 @@
 # RGMII PHY for Spartan-6
 from liteeth.common import *
 
-from litex.gen.genlib.io import DDROutput
-from litex.gen.genlib.misc import WaitTimer
-from litex.gen.genlib.fsm import FSM, NextState
+from migen.genlib.io import DDROutput
+from migen.genlib.misc import WaitTimer
+from migen.genlib.fsm import FSM, NextState
 
-from litex.gen.genlib.resetsync import AsyncResetSynchronizer
+from migen.genlib.resetsync import AsyncResetSynchronizer
 
 from liteeth.phy.common import *
 

liteeth/phy/s7rgmii.py

@@ -1,11 +1,11 @@
 # RGMII PHY for 7-Series Xilinx FPGA
 from liteeth.common import *
 
-from litex.gen.genlib.io import DDROutput
-from litex.gen.genlib.misc import WaitTimer
-from litex.gen.genlib.fsm import FSM, NextState
+from migen.genlib.io import DDROutput
+from migen.genlib.misc import WaitTimer
+from migen.genlib.fsm import FSM, NextState
 
-from litex.gen.genlib.resetsync import AsyncResetSynchronizer
+from migen.genlib.resetsync import AsyncResetSynchronizer
 
 from liteeth.phy.common import *
 

test/test_arp.py

@@ -1,5 +1,6 @@
 import unittest
-from litex.gen import *
+
+from migen import *
 
 from litex.soc.interconnect import wishbone
 from litex.soc.interconnect.stream_sim import *

test/test_etherbone.py

@@ -1,5 +1,6 @@
 import unittest
-from litex.gen import *
+
+from migen import *
 
 from litex.soc.interconnect import wishbone
 from litex.soc.interconnect.stream_sim import *

test/test_icmp.py

@@ -1,5 +1,6 @@
 import unittest
-from litex.gen import *
+
+from migen import *
 
 from litex.soc.interconnect import wishbone
 from litex.soc.interconnect.stream_sim import *

test/test_ip.py

@@ -1,5 +1,6 @@
 import unittest
-from litex.gen import *
+
+from migen import *
 
 from litex.soc.interconnect import wishbone
 from litex.soc.interconnect.stream_sim import *

test/test_mac_core.py

@@ -1,5 +1,6 @@
 import unittest
-from litex.gen import *
+
+from migen import *
 
 from litex.soc.interconnect import wishbone
 from litex.soc.interconnect.stream_sim import *

test/test_mac_wishbone.py

@@ -1,5 +1,6 @@
 import unittest
-from litex.gen import *
+
+from migen import *
 
 from litex.soc.interconnect import wishbone
 from litex.soc.interconnect.stream_sim import *

test/test_udp.py

@@ -1,5 +1,6 @@
 import unittest
-from litex.gen import *
+
+from migen import *
 
 from litex.soc.interconnect import wishbone
 from litex.soc.interconnect.stream_sim import *