diff --git a/example_designs/make.py b/example_designs/make.py
index 09cee59..241e69c 100755
--- a/example_designs/make.py
+++ b/example_designs/make.py
@@ -7,8 +7,8 @@ import subprocess
 import struct
 import importlib
 
-from litex.gen.fhdl import verilog
-from litex.gen.fhdl.structure import _Fragment
+from migen.fhdl import verilog
+from migen.fhdl.structure import _Fragment
 
 from litex.build.tools import write_to_file
 from litex.build.xilinx.common import *
diff --git a/example_designs/targets/base.py b/example_designs/targets/base.py
index 485109a..f0f3d08 100644
--- a/example_designs/targets/base.py
+++ b/example_designs/targets/base.py
@@ -1,4 +1,4 @@
-from litex.gen.genlib.io import CRG
+from migen.genlib.io import CRG
 
 from litex.build.xilinx.vivado import XilinxVivadoToolchain
 from litex.soc.interconnect import wishbone
diff --git a/example_designs/targets/core.py b/example_designs/targets/core.py
index 51afc06..cca1c3b 100644
--- a/example_designs/targets/core.py
+++ b/example_designs/targets/core.py
@@ -2,7 +2,7 @@
 
 import argparse
 
-from litex.gen import *
+from migen import *
 
 from litex.build.generic_platform import *
 from litex.build.xilinx.platform import XilinxPlatform
diff --git a/liteeth/common.py b/liteeth/common.py
index a765623..d54130a 100644
--- a/liteeth/common.py
+++ b/liteeth/common.py
@@ -1,6 +1,6 @@
 from math import ceil
 
-from litex.gen import *
+from migen import *
 
 from litex.soc.interconnect import stream
 from litex.soc.interconnect.stream import EndpointDescription
diff --git a/liteeth/core/arp.py b/liteeth/core/arp.py
index 68632c3..3495cdd 100644
--- a/liteeth/core/arp.py
+++ b/liteeth/core/arp.py
@@ -1,6 +1,7 @@
 from liteeth.common import *
 
-from litex.gen.genlib.misc import WaitTimer
+from migen.genlib.misc import WaitTimer
+
 from litex.soc.interconnect.stream_packet import Depacketizer, Packetizer
 
 
diff --git a/liteeth/core/mac/core.py b/liteeth/core/mac/core.py
index 2ec5870..b25d2f6 100644
--- a/liteeth/core/mac/core.py
+++ b/liteeth/core/mac/core.py
@@ -1,7 +1,8 @@
 from liteeth.common import *
 from liteeth.core.mac import gap, preamble, crc, padding, last_be
 from liteeth.phy.model import LiteEthPHYModel
-from litex.gen.genlib.cdc import PulseSynchronizer
+
+from migen.genlib.cdc import PulseSynchronizer
 
 
 class LiteEthMACCore(Module, AutoCSR):
diff --git a/liteeth/core/mac/crc.py b/liteeth/core/mac/crc.py
index fb0e0bc..3ddad49 100644
--- a/liteeth/core/mac/crc.py
+++ b/liteeth/core/mac/crc.py
@@ -4,7 +4,7 @@ from collections import OrderedDict
 
 from liteeth.common import *
 
-from litex.gen.genlib.misc import chooser, WaitTimer
+from migen.genlib.misc import chooser, WaitTimer
 
 
 class LiteEthMACCRCEngine(Module):
diff --git a/liteeth/core/mac/preamble.py b/liteeth/core/mac/preamble.py
index 3f17805..e3420a2 100644
--- a/liteeth/core/mac/preamble.py
+++ b/liteeth/core/mac/preamble.py
@@ -1,6 +1,6 @@
 from liteeth.common import *
 
-from litex.gen.genlib.misc import chooser
+from migen.genlib.misc import chooser
 
 
 class LiteEthMACPreambleInserter(Module):
diff --git a/liteeth/core/mac/wishbone.py b/liteeth/core/mac/wishbone.py
index 96fecf7..1aebfc8 100644
--- a/liteeth/core/mac/wishbone.py
+++ b/liteeth/core/mac/wishbone.py
@@ -1,8 +1,9 @@
+from migen.fhdl.simplify import FullMemoryWE
+
 from liteeth.common import *
 from liteeth.core.mac import sram
 
 from litex.soc.interconnect import wishbone
-from litex.gen.fhdl.simplify import FullMemoryWE
 
 
 class LiteEthMACWishboneInterface(Module, AutoCSR):
diff --git a/liteeth/phy/common.py b/liteeth/phy/common.py
index 9268fba..55f5207 100644
--- a/liteeth/phy/common.py
+++ b/liteeth/phy/common.py
@@ -1,7 +1,7 @@
 from liteeth.common import *
 
-from litex.gen.genlib.cdc import MultiReg
-from litex.gen.fhdl.specials import Tristate
+from migen.genlib.cdc import MultiReg
+from migen.fhdl.specials import Tristate
 
 class LiteEthPHYHWReset(Module):
     def __init__(self):
diff --git a/liteeth/phy/gmii.py b/liteeth/phy/gmii.py
index b0a2486..9f3180d 100644
--- a/liteeth/phy/gmii.py
+++ b/liteeth/phy/gmii.py
@@ -1,7 +1,7 @@
 from liteeth.common import *
 
-from litex.gen.genlib.io import DDROutput
-from litex.gen.genlib.resetsync import AsyncResetSynchronizer
+from migen.genlib.io import DDROutput
+from migen.genlib.resetsync import AsyncResetSynchronizer
 
 from liteeth.phy.common import *
 
diff --git a/liteeth/phy/gmii_mii.py b/liteeth/phy/gmii_mii.py
index 8fec464..cce200b 100644
--- a/liteeth/phy/gmii_mii.py
+++ b/liteeth/phy/gmii_mii.py
@@ -3,8 +3,8 @@ from liteeth.phy.gmii import LiteEthPHYGMIICRG
 from liteeth.phy.mii import LiteEthPHYMIITX, LiteEthPHYMIIRX
 from liteeth.phy.gmii import LiteEthPHYGMIITX, LiteEthPHYGMIIRX
 
-from litex.gen.genlib.io import DDROutput
-from litex.gen.genlib.cdc import PulseSynchronizer
+from migen.genlib.io import DDROutput
+from migen.genlib.cdc import PulseSynchronizer
 
 from litex.soc.interconnect.stream import Multiplexer, Demultiplexer
 
diff --git a/liteeth/phy/mii.py b/liteeth/phy/mii.py
index 635f8f9..d4c73d6 100644
--- a/liteeth/phy/mii.py
+++ b/liteeth/phy/mii.py
@@ -1,6 +1,6 @@
 from liteeth.common import *
 
-from litex.gen.genlib.resetsync import AsyncResetSynchronizer
+from migen.genlib.resetsync import AsyncResetSynchronizer
 
 from liteeth.phy.common import *
 
diff --git a/liteeth/phy/rmii.py b/liteeth/phy/rmii.py
index 49a8366..c387229 100644
--- a/liteeth/phy/rmii.py
+++ b/liteeth/phy/rmii.py
@@ -1,9 +1,9 @@
 from liteeth.common import *
 
-from litex.gen.genlib.cdc import MultiReg
-from litex.gen.genlib.misc import WaitTimer
-from litex.gen.genlib.io import DDROutput
-from litex.gen.genlib.resetsync import AsyncResetSynchronizer
+from migen.genlib.cdc import MultiReg
+from migen.genlib.misc import WaitTimer
+from migen.genlib.io import DDROutput
+from migen.genlib.resetsync import AsyncResetSynchronizer
 
 from liteeth.phy.common import *
 
diff --git a/liteeth/phy/s6rgmii.py b/liteeth/phy/s6rgmii.py
index 8d76b6e..854ddc2 100644
--- a/liteeth/phy/s6rgmii.py
+++ b/liteeth/phy/s6rgmii.py
@@ -1,11 +1,11 @@
 # RGMII PHY for Spartan-6
 from liteeth.common import *
 
-from litex.gen.genlib.io import DDROutput
-from litex.gen.genlib.misc import WaitTimer
-from litex.gen.genlib.fsm import FSM, NextState
+from migen.genlib.io import DDROutput
+from migen.genlib.misc import WaitTimer
+from migen.genlib.fsm import FSM, NextState
 
-from litex.gen.genlib.resetsync import AsyncResetSynchronizer
+from migen.genlib.resetsync import AsyncResetSynchronizer
 
 from liteeth.phy.common import *
 
diff --git a/liteeth/phy/s7rgmii.py b/liteeth/phy/s7rgmii.py
index 3d3c7d4..01b343c 100644
--- a/liteeth/phy/s7rgmii.py
+++ b/liteeth/phy/s7rgmii.py
@@ -1,11 +1,11 @@
 # RGMII PHY for 7-Series Xilinx FPGA
 from liteeth.common import *
 
-from litex.gen.genlib.io import DDROutput
-from litex.gen.genlib.misc import WaitTimer
-from litex.gen.genlib.fsm import FSM, NextState
+from migen.genlib.io import DDROutput
+from migen.genlib.misc import WaitTimer
+from migen.genlib.fsm import FSM, NextState
 
-from litex.gen.genlib.resetsync import AsyncResetSynchronizer
+from migen.genlib.resetsync import AsyncResetSynchronizer
 
 from liteeth.phy.common import *
 
diff --git a/test/test_arp.py b/test/test_arp.py
index 56dfdd3..d4e0b68 100644
--- a/test/test_arp.py
+++ b/test/test_arp.py
@@ -1,5 +1,6 @@
 import unittest
-from litex.gen import *
+
+from migen import *
 
 from litex.soc.interconnect import wishbone
 from litex.soc.interconnect.stream_sim import *
diff --git a/test/test_etherbone.py b/test/test_etherbone.py
index 8692089..3e9edc8 100644
--- a/test/test_etherbone.py
+++ b/test/test_etherbone.py
@@ -1,5 +1,6 @@
 import unittest
-from litex.gen import *
+
+from migen import *
 
 from litex.soc.interconnect import wishbone
 from litex.soc.interconnect.stream_sim import *
diff --git a/test/test_icmp.py b/test/test_icmp.py
index e4fb0da..e14ba33 100644
--- a/test/test_icmp.py
+++ b/test/test_icmp.py
@@ -1,5 +1,6 @@
 import unittest
-from litex.gen import *
+
+from migen import *
 
 from litex.soc.interconnect import wishbone
 from litex.soc.interconnect.stream_sim import *
diff --git a/test/test_ip.py b/test/test_ip.py
index 3a4bf65..1857555 100644
--- a/test/test_ip.py
+++ b/test/test_ip.py
@@ -1,5 +1,6 @@
 import unittest
-from litex.gen import *
+
+from migen import *
 
 from litex.soc.interconnect import wishbone
 from litex.soc.interconnect.stream_sim import *
diff --git a/test/test_mac_core.py b/test/test_mac_core.py
index 28102b8..10c2c08 100644
--- a/test/test_mac_core.py
+++ b/test/test_mac_core.py
@@ -1,5 +1,6 @@
 import unittest
-from litex.gen import *
+
+from migen import *
 
 from litex.soc.interconnect import wishbone
 from litex.soc.interconnect.stream_sim import *
diff --git a/test/test_mac_wishbone.py b/test/test_mac_wishbone.py
index 8d68062..1aa2fbc 100644
--- a/test/test_mac_wishbone.py
+++ b/test/test_mac_wishbone.py
@@ -1,5 +1,6 @@
 import unittest
-from litex.gen import *
+
+from migen import *
 
 from litex.soc.interconnect import wishbone
 from litex.soc.interconnect.stream_sim import *
diff --git a/test/test_udp.py b/test/test_udp.py
index 3884a97..b6b813b 100644
--- a/test/test_udp.py
+++ b/test/test_udp.py
@@ -1,5 +1,6 @@
 import unittest
-from litex.gen import *
+
+from migen import *
 
 from litex.soc.interconnect import wishbone
 from litex.soc.interconnect.stream_sim import *