Hardware
/
liteeth
mirror of https://github.com/enjoy-digital/liteeth.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Make memory/CSR regions customizable in config 

Also remove interrupt mapping, since it's unused without a CPU anyway.
This commit is contained in:
Xiretza 2020-02-12 15:10:59 +01:00
parent ca9cbd1555
commit 7a44209f77
No known key found for this signature in database
GPG Key ID: E51A6C6A1EB378ED
2 changed files with 6 additions and 10 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
examples/wishbone_mii.yml
View File

@ -8,3 +8,6 @@ vendor: xilinx
clk_freq: 100e6 clk_freq: 100e6
core: wishbone core: wishbone
endianness: big endianness: big
mem_map:
ethmac: 0x50000000

13
liteeth/gen.py
View File

@ -193,17 +193,10 @@ class PHYCore(SoCMini):
# MAC Core ----------------------------------------------------------------------------------------- # MAC Core -----------------------------------------------------------------------------------------
class MACCore(PHYCore): class MACCore(PHYCore):
interrupt_map = SoCCore.interrupt_map
interrupt_map.update({
"ethmac": 2,
})
mem_map = SoCCore.mem_map
mem_map.update({
"ethmac": 0x50000000
})
def __init__(self, platform, core_config): def __init__(self, platform, core_config):
self.mem_map.update(core_config.get("mem_map", {}))
self.csr_map.update(core_config.get("csr_map", {}))
PHYCore.__init__(self, core_config["phy"], core_config["clk_freq"], platform) PHYCore.__init__(self, core_config["phy"], core_config["clk_freq"], platform)
self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", endianness=core_config["endianness"]) self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", endianness=core_config["endianness"])