diff --git a/example_designs/make.py b/example_designs/make.py index dcd1c19..ddf6290 100644 --- a/example_designs/make.py +++ b/example_designs/make.py @@ -7,8 +7,8 @@ import subprocess import struct import importlib -from migen.fhdl import verilog -from migen.fhdl.structure import _Fragment +from litex.gen.fhdl import verilog +from litex.gen.fhdl.structure import _Fragment from litex.build.tools import write_to_file from litex.build.xilinx.common import * diff --git a/example_designs/targets/base.py b/example_designs/targets/base.py index 7858846..d7e168c 100644 --- a/example_designs/targets/base.py +++ b/example_designs/targets/base.py @@ -1,5 +1,5 @@ -from migen.genlib.io import CRG -from migen.fhdl.specials import Keep +from litex.gen.genlib.io import CRG +from litex.gen.fhdl.specials import Keep from litex.build.xilinx.vivado import XilinxVivadoToolchain from litex.soc.interconnect import wishbone diff --git a/liteeth/common.py b/liteeth/common.py index 9c3fd19..8e2479c 100644 --- a/liteeth/common.py +++ b/liteeth/common.py @@ -1,11 +1,11 @@ import math from collections import OrderedDict -from migen import * -from migen.genlib.resetsync import AsyncResetSynchronizer -from migen.genlib.record import * -from migen.genlib.fsm import FSM, NextState -from migen.genlib.misc import chooser, WaitTimer +from litex.gen import * +from litex.gen.genlib.resetsync import AsyncResetSynchronizer +from litex.gen.genlib.record import * +from litex.gen.genlib.fsm import FSM, NextState +from litex.gen.genlib.misc import chooser, WaitTimer from litex.soc.interconnect.stream import * from litex.soc.interconnect.packet import * diff --git a/liteeth/core/mac/frontend/wishbone.py b/liteeth/core/mac/frontend/wishbone.py index 3c0e093..bad329f 100644 --- a/liteeth/core/mac/frontend/wishbone.py +++ b/liteeth/core/mac/frontend/wishbone.py @@ -2,7 +2,7 @@ from liteeth.common import * from litex.soc.cores.liteeth_mini.mac.frontend import sram from litex.soc.interconnect import wishbone -from migen.fhdl.simplify import FullMemoryWE +from litex.gen.fhdl.simplify import FullMemoryWE class LiteEthMACWishboneInterface(Module, AutoCSR): diff --git a/liteeth/phy/gmii.py b/liteeth/phy/gmii.py index 8a6aa94..46e6d93 100644 --- a/liteeth/phy/gmii.py +++ b/liteeth/phy/gmii.py @@ -1,4 +1,4 @@ -from migen.genlib.io import DDROutput +from litex.gen.genlib.io import DDROutput from liteeth.common import * diff --git a/liteeth/phy/gmii_mii.py b/liteeth/phy/gmii_mii.py index 607b247..1b5613f 100644 --- a/liteeth/phy/gmii_mii.py +++ b/liteeth/phy/gmii_mii.py @@ -1,5 +1,5 @@ -from migen.genlib.io import DDROutput -from migen.genlib.cdc import PulseSynchronizer +from litex.gen.genlib.io import DDROutput +from litex.gen.genlib.cdc import PulseSynchronizer from litex.soc.interconnect.stream import Multiplexer, Demultiplexer diff --git a/liteeth/phy/s6rgmii.py b/liteeth/phy/s6rgmii.py index 60e6d83..8f7eaa9 100644 --- a/liteeth/phy/s6rgmii.py +++ b/liteeth/phy/s6rgmii.py @@ -1,8 +1,8 @@ # RGMII PHY for Spartan-6 -from migen.genlib.io import DDROutput -from migen.genlib.misc import WaitTimer -from migen.genlib.fsm import FSM, NextState +from litex.gen.genlib.io import DDROutput +from litex.gen.genlib.misc import WaitTimer +from litex.gen.genlib.fsm import FSM, NextState from liteeth.common import * diff --git a/test/arp_tb.py b/test/arp_tb.py index 3b9c355..be482a7 100644 --- a/test/arp_tb.py +++ b/test/arp_tb.py @@ -1,7 +1,7 @@ -from migen.fhdl.std import * -from migen.bus import wishbone -from migen.bus.transactions import * -from migen.sim.generic import run_simulation +from litex.gen.fhdl.std import * +from litex.gen.bus import wishbone +from litex.gen.bus.transactions import * +from litex.gen.sim.generic import run_simulation from liteeth.common import * from liteeth.core.mac import LiteEthMAC diff --git a/test/common.py b/test/common.py index e26426c..a2f2486 100644 --- a/test/common.py +++ b/test/common.py @@ -1,9 +1,9 @@ import random import copy -from migen.fhdl.std import * -from migen.flow.actor import Sink, Source -from migen.genlib.record import * +from litex.gen.fhdl.std import * +from litex.gen.flow.actor import Sink, Source +from litex.gen.genlib.record import * from liteeth.common import * diff --git a/test/etherbone_tb.py b/test/etherbone_tb.py index 15cf61b..4f19f2a 100644 --- a/test/etherbone_tb.py +++ b/test/etherbone_tb.py @@ -1,7 +1,7 @@ -from migen.fhdl.std import * -from migen.bus import wishbone -from migen.bus.transactions import * -from migen.sim.generic import run_simulation +from litex.gen.fhdl.std import * +from litex.gen.bus import wishbone +from litex.gen.bus.transactions import * +from litex.gen.sim.generic import run_simulation from liteeth.common import * from liteeth.core import LiteEthUDPIPCore diff --git a/test/icmp_tb.py b/test/icmp_tb.py index 616c09b..8a2f0f8 100644 --- a/test/icmp_tb.py +++ b/test/icmp_tb.py @@ -1,7 +1,7 @@ -from migen.fhdl.std import * -from migen.bus import wishbone -from migen.bus.transactions import * -from migen.sim.generic import run_simulation +from litex.gen.fhdl.std import * +from litex.gen.bus import wishbone +from litex.gen.bus.transactions import * +from litex.gen.sim.generic import run_simulation from liteeth.common import * from liteeth.core import LiteEthIPCore diff --git a/test/ip_tb.py b/test/ip_tb.py index 3b6a96a..b1c7fe3 100644 --- a/test/ip_tb.py +++ b/test/ip_tb.py @@ -1,7 +1,7 @@ -from migen.fhdl.std import * -from migen.bus import wishbone -from migen.bus.transactions import * -from migen.sim.generic import run_simulation +from litex.gen.fhdl.std import * +from litex.gen.bus import wishbone +from litex.gen.bus.transactions import * +from litex.gen.sim.generic import run_simulation from liteeth.common import * from liteeth.core import LiteEthIPCore diff --git a/test/mac_core_tb.py b/test/mac_core_tb.py index 8d2e37b..a684dcc 100644 --- a/test/mac_core_tb.py +++ b/test/mac_core_tb.py @@ -1,7 +1,7 @@ -from migen.fhdl.std import * -from migen.bus import wishbone -from migen.bus.transactions import * -from migen.sim.generic import run_simulation +from litex.gen.fhdl.std import * +from litex.gen.bus import wishbone +from litex.gen.bus.transactions import * +from litex.gen.sim.generic import run_simulation from liteeth.common import * from liteeth.core.mac.core import LiteEthMACCore diff --git a/test/mac_wishbone_tb.py b/test/mac_wishbone_tb.py index 1826bb2..7c69fed 100644 --- a/test/mac_wishbone_tb.py +++ b/test/mac_wishbone_tb.py @@ -1,7 +1,7 @@ -from migen.fhdl.std import * -from migen.bus import wishbone -from migen.bus.transactions import * -from migen.sim.generic import run_simulation +from litex.gen.fhdl.std import * +from litex.gen.bus import wishbone +from litex.gen.bus.transactions import * +from litex.gen.sim.generic import run_simulation from liteeth.common import * from liteeth.core.mac import LiteEthMAC diff --git a/test/udp_tb.py b/test/udp_tb.py index f8f6981..ffc95fa 100644 --- a/test/udp_tb.py +++ b/test/udp_tb.py @@ -1,7 +1,7 @@ -from migen.fhdl.std import * -from migen.bus import wishbone -from migen.bus.transactions import * -from migen.sim.generic import run_simulation +from litex.gen.fhdl.std import * +from litex.gen.bus import wishbone +from litex.gen.bus.transactions import * +from litex.gen.sim.generic import run_simulation from liteeth.common import * from liteeth.core import LiteEthUDPIPCore