test: use passive generators and some cleanup
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@ -1,3 +1,4 @@
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#!/usr/bin/env python3
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from litex.gen import *
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from litex.soc.interconnect import wishbone
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@ -34,10 +35,6 @@ def main_generator(dut):
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yield
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print("Received MAC : 0x{:12x}".format((yield dut.arp.table.response.mac_address)))
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# XXX: find a way to exit properly
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import sys
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sys.exit()
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if __name__ == "__main__":
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tb = TB()
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generators = {
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#!/usr/bin/env python3
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from litex.gen import *
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from litex.soc.interconnect import wishbone
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@ -96,10 +97,6 @@ def main_generator(dut):
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s, l, e = check(writes_datas, loopback_writes_datas)
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print("shift " + str(s) + " / length " + str(l) + " / errors " + str(e))
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# XXX: find a way to exit properly
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import sys
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sys.exit()
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if __name__ == "__main__":
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tb = TB()
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generators = {
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#!/usr/bin/env python3
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from litex.gen import *
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from litex.soc.interconnect import wishbone
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@ -38,10 +39,6 @@ def main_generator(dut):
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for i in range(256):
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yield
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# XXX: find a way to exit properly
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import sys
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sys.exit()
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if __name__ == "__main__":
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tb = TB()
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generators = {
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#!/usr/bin/env python3
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from litex.gen import *
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from litex.soc.interconnect import wishbone
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@ -23,20 +24,15 @@ class TB(Module):
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self.ip_port = self.ip.ip.crossbar.get_port(udp_protocol)
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def main_generator(dut):
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while True:
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yield dut.ip_port.sink.valid.eq(1)
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yield dut.ip_port.sink.last.eq(1)
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yield dut.ip_port.sink.ip_address.eq(0x12345678)
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yield dut.ip_port.sink.protocol.eq(udp_protocol)
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yield dut.ip_port.source.ready.eq(1)
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if (yield dut.ip_port.source.valid) == 1 and (yield dut.ip_port.source.last) == 1:
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print("packet from IP 0x{:08x}".format((yield dut.ip_port.sink.ip_address)))
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# XXX: find a way to exit properly
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import sys
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sys.exit()
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yield dut.ip_port.sink.valid.eq(1)
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yield dut.ip_port.sink.last.eq(1)
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yield dut.ip_port.sink.ip_address.eq(0x12345678)
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yield dut.ip_port.sink.protocol.eq(udp_protocol)
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yield dut.ip_port.source.ready.eq(1)
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while not ((yield dut.ip_port.source.valid) and (yield dut.ip_port.source.last)):
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yield
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print("packet from IP 0x{:08x}".format((yield dut.ip_port.sink.ip_address)))
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if __name__ == "__main__":
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tb = TB()
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#!/usr/bin/env python3
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from litex.gen import *
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from litex.soc.interconnect import wishbone
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@ -16,9 +17,9 @@ class TB(Module):
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self.submodules.core = LiteEthMACCore(phy=self.phy_model, dw=8, with_preamble_crc=True)
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self.submodules.streamer = PacketStreamer(eth_phy_description(8), last_be=1)
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self.submodules.streamer_randomizer = AckRandomizer(eth_phy_description(8), level=50)
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self.submodules.streamer_randomizer = Randomizer(eth_phy_description(8), level=50)
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self.submodules.logger_randomizer = AckRandomizer(eth_phy_description(8), level=50)
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self.submodules.logger_randomizer = Randomizer(eth_phy_description(8), level=50)
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self.submodules.logger = PacketLogger(eth_phy_description(8))
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self.comb += [
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@ -43,10 +44,6 @@ def main_generator(dut):
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s, l, e = check(packet, dut.logger.packet)
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print("shift " + str(s) + " / length " + str(l) + " / errors " + str(e))
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# XXX: find a way to exit properly
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import sys
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sys.exit()
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if __name__ == "__main__":
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tb = TB()
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generators = {
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#!/usr/bin/env python3
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from litex.gen import *
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from litex.soc.interconnect import wishbone
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@ -111,9 +112,6 @@ def main_generator(dut):
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dat = int.from_bytes(tx_payload[4*i:4*(i+1)], "big")
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yield from wishbone_master.write(sram_reader_slots_offset[slot]+i, dat)
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# XXX: find a way to exit properly
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import sys
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sys.exit()
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# # send tx payload & wait
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# yield from sram_reader_driver.start(slot, length)
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@ -54,6 +54,7 @@ class PHY(Module):
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print_phy(r)
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self.packet = self.phy_sink.packet
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@passive
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def generator(self):
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while True:
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yield from self.receive()
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@ -1,3 +1,4 @@
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#!/usr/bin/env python3
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from litex.gen import *
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from litex.soc.interconnect import wishbone
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@ -43,10 +44,6 @@ def main_generator(dut):
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s, l, e = check(packet, dut.logger.packet)
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print("shift " + str(s) + " / length " + str(l) + " / errors " + str(e))
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# XXX: find a way to exit properly
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import sys
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sys.exit()
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if __name__ == "__main__":
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tb = TB(8)
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generators = {
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