From 7f4df176158559acbc3961b2986526c33cecca86 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Thu, 8 Jun 2023 22:04:18 +0200 Subject: [PATCH] liteeth_gen: Add initial (and wip) etherbone support. --- liteeth/gen.py | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/liteeth/gen.py b/liteeth/gen.py index a85011c..06ed270 100755 --- a/liteeth/gen.py +++ b/liteeth/gen.py @@ -47,6 +47,8 @@ from liteeth import phy as liteeth_phys from liteeth.mac import LiteEthMAC from liteeth.core import LiteEthUDPIPCore +from liteeth.frontend.etherbone import LiteEthEtherbone + # IOs ---------------------------------------------------------------------------------------------- _io = [ @@ -306,6 +308,19 @@ class UDPCore(PHYCore): with_sys_datapath = (data_width == 32), ) + # Etherbone -------------------------------------------------------------------------------- + + # /!\ WIP /!\ + with_etherbone = True + if with_etherbone: + assert (data_width == 32) + self.submodules.etherbone = LiteEthEtherbone(self.core.udp, 1234, buffer_depth=16, cd="sys") + axil_bus = axi.AXILiteInterface(address_width=32, data_width=32) + platform.add_extension(axil_bus.get_ios("mmap")) + self.submodules += axi.Wishbone2AXILite(self.etherbone.wishbone.bus, axil_bus) + self.comb += axil_bus.connect_to_pads(platform.request("mmap"), mode="master") + # /!\ WIP /!\ + # UDP Ports -------------------------------------------------------------------------------- for name, port in core_config["udp_ports"].items(): # Parameters.